PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 95

• Manufacturer Part Number: PSB3186FV14XP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 53
3.7.5
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
Both arbitration mechanisms are implemented in the ISAC-SX TE and will be described
in the following two chapters.
3.7.5.1
The TIC bus is imlemented to organize the access to the layer-1 functions provided in
the ISAC-SX TE (C/I-channel) and to the D-channel from up to 7 external communication
controllers
Note: If the TIC Bus feature is not used, it has to be switched off in order not to
To this effect the outputs of the D-channel controllers (e.g. ICC - ISDN Communication
Controller PEB 2070) are wired-or (negative logic, i.e. a “0” wins) and connected to pin
DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/
DD are required. The arbitration mechanism must be activated by setting
MODED.DIM2-0=00x.
Data Sheet
multipoint configuration (NT ® TE1 … TE8).
disturb the layer-1 control and the HDLC controller. This is done by setting
bit DIM 1 in register Mode D and bit 4 in register IOM_CR. For more details
please refer to the application note “Reconfigurable PBX”.
(Figure
D-Channel Access Control
TIC Bus D-Channel Access Control
CIC Interrupt Structure
TRAN
MASK
WOV
MOS
ICD
CIC
ST
Interrupt
54).
TRAN
ISTA
WOV
MOS
ICD
CIC
ST
95
CI1E
CIX1
Description of Functional Blocks
CIC0
CIC1
CIR0
ISAC-SX TE
PSB 3186
2003-01-30