PSB3186FV14XT Infineon Technologies, PSB3186FV14XT Datasheet - Page 103

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Operating Modes
There are 5 different operating modes which can be selected via the mode selection bits
MDS2-0 in the MODED registers:
Non-Auto Mode (MDS2-0 = ’01x’)
Characteristics:
All frames with valid addresses are accepted and the bytes following the address are
transferred to the m P via RFIFOD. Additional information is available in RSTAD.
Transparent mode 0 (MDS2-0 = ’110’).
Characteristics:
Every received frame is stored in RFIFOD (first byte after opening flag to CRC field).
Additional information can be read from RSTAD.
Transparent mode 1 (MDS2-0 = ’111’).
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
RFIFOD. Additional information can be read from RSTAD.
Transparent mode 2 (MDS2-0 = ’101’).
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
RFIFOD. Additional information is available in RSTAD.
Extended transparent mode (MDS2-0 = ’100’).
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to
Data Sheet
Chapter
H
/FC
Full address recognition with one-byte (MDS = ’010’) or
two-byte (MDS = ’011’) address comparison
no address recognition
SAPI recognition
TEI recognition
fully transparent
3.8.5.
H
). In the case of a match, all the following bytes are stored in
H
). In case of a match the rest of the frame is stored in the
103
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30