PSB3186FV14XT Infineon Technologies, PSB3186FV14XT Datasheet - Page 159

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

STI
ASTI
4.3.9
Value after reset: 00
For all interrupts in the STI register the following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
The interrupts are automatically reset by reading the STI register. For general
information please refer to
STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
4.3.10
Value after reset: 00
For general information please refer to
Data Sheet
receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles.
7
7
STOV
STI - Synchronous Transfer Interrupt
ASTI - Acknowledge Synchronous Transfer Interrupt
21
0
STOV
H
H
20
0
Chapter
STOV
11
0
STOV
3.7.1.1.
10
0
Chapter
159
ACK
STI
21
21
3.7.1.1.
ACK
STI
20
20
Detailed Register Description
ACK
STI
11
11
0
0
ACK
STI
10
10
ISAC-SX TE
PSB 3186
2003-01-30
WR (58)
RD (58)