PSB3186FV14XT Infineon Technologies, PSB3186FV14XT Datasheet - Page 114

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

ISAC-SX TE
PSB 3186
Description of Functional Blocks
available space in the XFIFOD, so any number of bytes smaller than the selected XFBS
may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF, XME or XRES command. XRES resets the XFIFOD.
The XFIFOD can hold any number of frames fitting in the 64 bytes.
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller doesn’t react fast enough
to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes), in this case an XMR transmit message repeat
interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFOD. The XFIFOD is locked while
an XMR or XDU interrupt is pending, i.d. all write actions of the microcontroller will be
ignored as long as the microcontroller hasn’t read the ISTAD register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (block size), then the data in the
XFIFOD will be corrupted and the STARD.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDRD.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in
Figure
64.
Data Sheet
114
2003-01-30