DS26528G+ Maxim Integrated Products, DS26528G+ Datasheet - Page 54

• Manufacturer Part Number: DS26528G+
• Description: IC TXRX T1/E1/J1 OCT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26528G+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.9.4.5 Receive SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72-
frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008.
To enable the DS26528 to synchronize onto a SLC-96 pattern, the following configuration should be used:
The SLC-96 message bits can be extracted via the
at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has updated
the data link registers
RSLC96 bit is set, the user has 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data
from the
SLC-96 alignment pattern.
8.9.5 T1 Data Link
8.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller
The DS26528 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC
function is available only in T1 mode.
Table 8-18. Registers Related to T1 Transmit BOC
Transmit HDLC Control Register 2 (THC2)
Transmit Control Register 1(TCR1)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
Bits 0 to 5 in the
causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The
transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as
SBOC is set. Note that the TFPT (TCR1.6) control bit must be set to 0 for the BOC message to overwrite F-bit
information being sampled on TSER.
8.9.5.1.1 To Transmit a BOC
Transmit BOC Register (T1TBOC)
1) Write 6-bit code into the
2) Set SBOC bit in
•
•
•
•
T1RSLC1:T1RSLC3
RCR1.5 (RFM) = 1
RCR1.3 (SYNCC) = 1
T1RCR2.4 (RSLC96) = 1
RCR1.7 (SYNCT) = 0
REGISTER
T1TBOC
T1RSLC1:T1RSLC3
THC2
register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6)
registers. Note that RSLC96 will not set if the DS26528 is unable to detect the 12-bit
= 1.
T1TBOC
Table 8-18
Set to D4 framing mode.
Set to cross-couple Ft and Fs bits.
Enable SLC-96 synchronizer.
Set to minimum sync time.
register.
with the latest message data from the incoming data stream. Once the
ADDRESSES
shows the registers related to the transmit bit-oriented code.
FRAMER
163h
113h
181h
T1RSLC1:T1RSLC3
54 of 276
Transmit bit-oriented message code register.
Bit to enable sending of transmit BOC.
Determines the sourcing of the F-bit.
registers. The status bit RSLC96 located
DS26528 Octal T1/E1/J1 Transceiver
FUNCTION