MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 354

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2.31 PMF Frequency Control C Register (PMFFQCC)
Read anytime and write only if MTG is set.
354
Module Base + 0x0031
PWMRFC
LDFQC
PRSCC
HALFC
Reset
Field
7–4
3
2
0
W
R
LDFQC
0000
0001
0010
0011
0100
0101
0110
0111
Load Frequency C — This field selects the PWM load frequency according to
Section 11.4.7.2, “Load Frequency”
Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the load
Half Cycle Reload C — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
Prescaler C — This buffered field selects the PWM clock frequency illustrated in
Note: Reading the PRSCC field reads the buffered value and not necessarily the value currently in effect. The
PWM Reload Flag C — This flag is set at the beginning of every reload cycle regardless of the state of the
LDOKC bit. Clear PWMRFC by reading PMFFQCC with PWMRFC set and then writing a logic one to the
PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFC
has no effect.
0 No new reload cycle since last PWMRFC clearing
1 New reload cycle since last PWMRFC clearing
Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests.
0
7
okay bit, LDOKC. Reading the LDFQC field reads the buffered value and not necessarily the value
currently in effect.
PRSCC field takes effect at the beginning of the next PWM cycle and only when the load okay bit, LDOKC,
is set.
Figure 11-37. PMF Frequency Control C Register (PMFFQCC)
Every 2 PWM opportunities
Every 3 PWM opportunities
Every 4 PWM opportunities
Every 5 PWM opportunities
Every 6 PWM opportunities
Every 7 PWM opportunities
Every 8 PWM opportunities
0
6
PWM Reload Frequency
Every PWM opportunity
LDFQC
Table 11-40. PMFFQCC Field Descriptions
Table 11-41. PWM Reload Frequency C
MC9S12E128 Data Sheet, Rev. 1.07
0
5
for more details.
0
4
Description
LDFQ[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
HALFC
0
3
Every 10 PWM opportunities
Every 11 PWM opportunities
Every 12 PWM opportunities
Every 13 PWM opportunities
Every 14 PWM opportunities
Every 15 PWM opportunities
Every 16 PWM opportunities
Every 9 PWM opportunities
PWM Reload Frequency
0
2
PRSCC
Table
Table
11-41. See
Freescale Semiconductor
11-42.
0
1
PWMRFC
0
0