MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 487
MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
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16.3.2.7
1
2
Freescale Semiconductor
When BKABEN is set (BKP mode), all bits in DBGC2 are available. When BKABEN is cleared and DBG is used in DBG mode,
bits FULL and TAGAB have no meaning.
These bits can be used in BKP mode and DBG mode (when capture mode is not set in LOOP1) to provide a third breakpoint.
BKABEN
BKCEN
TAGAB
Reset
TAGC
Field
FULL
BDM
7
6
5
4
3
2
W
R
PAGSEL
BKABEN
x0
x1
Breakpoint Using Comparator A and B Enable — This bit enables the breakpoint capability using comparator
A and B, when set (BKP mode) the DBGEN bit in DBGC1 cannot be set.
0 Breakpoint module off
1 Breakpoint module on
Full Breakpoint Mode Enable — This bit controls whether the breakpoint module is in dual mode or full mode.
In full mode, comparator A is used to match address and comparator B is used to match data. See
Section 16.4.1.2, “Full Breakpoint
0 Dual address mode enabled
1 Full breakpoint mode enabled
Background Debug Mode Enable — This bit determines if the breakpoint causes the system to enter
background debug mode (BDM) or initiate a software interrupt (SWI).
0 Go to software interrupt on a break request
1 Go to BDM on a break request
Comparator A/B Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Breakpoint Comparator C Enable Bit — This bit enables the breakpoint capability using comparator C.
0 Comparator C disabled for breakpoint
1 Comparator C enabled for breakpoint
Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode.
Comparator C Tag Select — This bit controls whether the breakpoint will cause a break on the next instruction
boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause
a tagged breakpoint.
0 On match, break at the next instruction boundary (force)
1 On match, break if/when the instruction is about to be executed (tagged)
Debug Control Register 2 (DBGC2)
0
7
1
FULL
0
6
Figure 16-13. Debug Control Register 2 (DBGC2)
Table 16-14. DBGC2 Field Descriptions
Table 16-13. Comparator C Compares
EXTCMP[5:0] = XAB[21:16]
BDM
MC9S12E128 Data Sheet, Rev. 1.07
EXTCMP Compare
0
5
Mode,” for more details.
No compare
TAGAB
0
4
Description
BKCEN
0
3
2
DBGCCH[7:0] = XAB[15:14],AB[13:8]
TAGC
0
2
DBGCCH[7:0] = AB[15:8]
High-Byte Compare
2
Chapter 16 Debug Module (DBGV1)
RWCEN
0
1
2
RWC
0
0
2
487
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