STA015B$ STMicroelectronics, STA015B$ Datasheet

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... S AND by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the most common DACs architectures used on the market. The func- tional STA015 chip partitioning is described in Fig.1a and Fig.1b. STA015 TQFP44 LFBGA64 STA015T$ (TQFP44) STA015B$ (LFBGA 8x8) 1/56 ...

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STA015 Figure 1. 1a. Block Diagram for TQFP44 and LFBGA64 package. TQFP44 34 SDI SERIAL 36 SCKR INPUT INTERFACE 38 BIT_EN 27 BUFFER DATA-REQ 256 SCK_ADC ADC 26 LRCK_ADC INPUT INTERFACE 24 SDI_ADC 25 RESET 1b. BLOCK ...

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Figure 2. Pin Connection SRC_INT/SCK_ADC LRCKT GPSO_REQ VSS_2 VDD_2 VSS_3 VDD_3 D00AU1149 VDD_1 1 28 VSS_1 2 27 SDA 3 26 SCL 4 25 SDI ...

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STA015 1.0 OVERVIEW 1.1 MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCIL- LARY data extraction: ...

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PIN DESCRIPTION SO28 TQFP44 LFBGA64 ...

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STA015 ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH ...

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... The STA015 input clock is derivated from an external source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz. Other frequencies may be supported upon request to STMicroelectronics. Each frequency is supported by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels. ...

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STA015 CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not ...

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This could be useful, for instance, to process audio data coming from an external tuner or some other auxiliary source. MP3 mode In MP3 Mode (default mode) STA015 decodes the incoming bitstream, acting as a master of the ...

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STA015 Init Mode "PLAY" and "MUTE" changes are ignored in this mode. The internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". The "init" phase ends when the ...

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BIT_EN line should be toggled only when SCKR is stable low (for both SCLK_POL con- figuration). The possible configurations are described in Fig. 8. 3.2 GPSO Output Interface In order to retrieve ADPCM encoded data a General Purpose ...

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STA015 3.4 ADC Inteface Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to interface with most A/D converters. To configure this interface 4 spe- ...

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Figure 11. LRCK_ADC SDI_ADC SCK_ADC SDI SCKR RECEIVER DATA_REQ The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as far as ADPCM en- coding function. As shown in the figures some configuration is not available ...

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STA015 Figure 14. Input from BITSTREAM, Output from GPSO MCU Figure 15. Input from ADC, Output from GPSO GPSO_DATA GPSO_SCKR MCU GPSO_REQ LRCK_ADC SCK_ADC ADC SDI_ADC MASTER 2 5 BUS SPECIFICATION 2 The STA015 supports the I C ...

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Data input During the data input the STA015 samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and ...

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STA015 5.4 READ OPERATION (see Fig. 17) 5.4.1 Current byte address read The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is in- cremented. For the current byte address read mode, ...

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I C REGISTERS $45 69 $46 70 $47 71 $48 72 $49 73 $4D 77 $4E 78 $50 80 $51 81 $52 82 $52 82 $53 83 $54 84 $55 85 $56 86 $61 97 $63 99 $64 100 ...

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STA015 6.1 STA015 REGISTERS DESCRIPTION The STA015 device includes 128 I scribed. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written. The following table describes ...

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UPD_FRAC: when is set to 1, update FRAC in the switching circuit set to 1 after autoboot. XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output ...

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STA015 SCKL_POL Address: 0x0D (13) Type: R/W Software Reset: 0x04 Hardware Reset: 0x04 MSB don’t care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If ...

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SOFT_RESET Address: 0x10 (16) Type: WO Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation reset When this register is written, a soft reset occours. The STA015 core ...

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STA015 CMD_INTERRUPT Address: 0x16 (22) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation write into I C/Ancillary Data The INTERRUPT is used to give ...

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ADPCM_DATA BUFFER Address: 0x40 - 0x51 (64 - 81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 ANCCOUNT_L Address: 0x41 (65) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 AC7 AC6 AC5 ANCCOUNT_H Address: ...

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STA015 HEAD_M[15:8] MSB b7 b6 H15 H14 H13 HEAD_L[7:0] MSB Address: 0x43, 0x44, 0x45 (67, 68, 69) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode ...

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Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. bitrate index ’0000’ ’0001’ ’0010’ ’0011’ ’0100’ ’0101’ ’0110’ ’0111’ ’1000’ ’1001’ ’1010’ ’1011’ ’1100’ ’1101’ ’1110’ ’1111’ Sampling Frequency indicates the sampling frequency of the encoded audio signal (KHz) ...

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STA015 Mode extension These bits are used in joint stereo mode. They indicates which type of joint stereo coding method is ap- plied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are applied, are im- plicit in the ...

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DLB Address: 0x47 (71) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DLB7 DLB6 DLB5 DLB4 DLB register is used to ...

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STA015 DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DRB7 DRB6 DRB5 DRB register is used to ...

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If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is neverthe- less affected with the value 0x01 if a discrepance has occurred. MFSDF_441 Address: 0x50 (80) Type: R/W Software Reset: 0x00 Hardware ...

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STA015 Hardware Reset: 0x00 MSB b7 b6 PF15 PF14 PF13 The registers are considered logically concatenated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H registers) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W ...

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PCM_DIV = (O_FAC/64 bit mode 5) PCM_DIV = (O_FAC/128 bit mode Example for setting: MSB PD7 PD6 PD5 PD4 ...

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STA015 PCMCONF is used to set the PCM Output Interface configuration: ORD: PCM order. If this bit is set to’1’, the LS Bit is transmitted first, otherwise MS Bit is transmiited first. DIF: PCM_DIFF used to select the ...

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PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB The default ...

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STA015 the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0]) MSB b7 b6 PF7 PF6 PF5 PLLFRAC_H ([15:8]) MSB b7 b6 PF15 PF14 PF13 Address: 0x64 - 0x65 (100 - 101) Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: ...

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Address: 0x67, 0x68, 0x69 (103 - 104 - 105) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically concatenated and compose the Global Frame Counter as de- scribed in the table updated at ...

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STA015 TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 TF7 TF6 TF5 TREBLE_FREQUENCY_HIGH Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 TF15 TF14 TF13 The registers TREBLE_FREQUENCY-HIGH and ...

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Bass_Freq <= Treble_Freq Bass_Freq > 0 (suggested range < Bass_Freq < 750 Hz) Example: Bass = 200Hz Treble = 3kHz TFS BFS ...

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STA015 BASS_ENHANCE Address: 0x7C (1240 Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 b6 BE7 BE6 BE5 Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at ...

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For example, in case signal (max. level) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in ...

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STA015 Hardware Reset: 0x00 MSB don’t care ancillary data 1 = Ancillary Data Available The ISR is used by the microcontroller to understand when a new ancillary data block is available. ...

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GPSO_ENABLE Address: 0xB9 (185) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB This register enable/disable the GPSO interface. Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to ...

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STA015 ADC_CONF Address: 0xBC (188) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB Using this register the ADC input interface can be configured as follow: 2 AIIS: ADC I S mode 0 = sample word ...

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ADPCM_FRAME_SIZE Address: 0xBD (189) Type: R/W Software Reset: 0x13 Hardware Reset: 0x00 MSB b7 b6 AFS7 AFS6 AFS5 The ADPCM frame size may be adjusted to match a trade-off between the bitrate overhead and the frame length. The frame size ...

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STA015 ADC_WLEN Address: 0xC0 (192) Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F MSB select ADC word length AWL4 through AWL0 bits can be used. This 5 bit value must contain the size of the ...

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I/O CELL DESCRIPTION (pinout relative to TQFP44 package) 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42 CMOS Bidir Pad Buffer, 4mA, with Slew ...

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STA015 6.3 TIMING DIAGRAMS 6.3.1 Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT) SDO SCKT LRCLK tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + ...

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Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns 6.3.2 Bitstream input interface (SDI, SCKR, BIT_EN) ...

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STA015 6.3.5 XTI,XTO and CLK_OUT timings XTI (INPUT) XTO t xto CLK_OUT t clk_out txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, ...

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Table 2. PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 3. PLL Configuration Sequence For ...

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STA015 Table 6. PLL Configuration Sequence For 14.31818MHz Input Clock 512 Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 7. PLL Configuration Sequence ...

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STA015 CONFIGURATION FILE FORMAT The STA015 Configuration File is an ASCII format. An example of the file format is the following 128 15 ............ sequence of rows and each one can be ...

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STA015 mm DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 c1 45° (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 ...

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DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 D3 8.00 E 11.80 ...

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STA015 mm DIM. MIN. TYP. MAX. MIN. A 1.700 A1 0.350 0.400 0.450 0.014 A2 1.100 b 0.500 D 8.000 D1 5.600 e 0.800 E 8.000 E1 5.600 f 1.200 BALL 1 IDENTIFICATION ...

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REVISION HISTORY Date Revision 16-Mar-2004 4 Changed block diagram pin 28, changed legalcy 26-Apr-2010 5 Major revision for revalidation process Changes STA015 55/56 ...

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... STA015 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...