STA015B$ STMicroelectronics, STA015B$ Datasheet - Page 8

• Manufacturer Part Number: STA015B$
• Description: DECODER AUDIO MPEG 2.5 8X8LFBGA
• Manufacturer: STMicroelectronics
• Type: Audio Decoderr

Specifications of STA015B$

• Applications: Sound Cards, Players, Recorders
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -

STA015
CMOS compatibility
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS
pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if V
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
2.2 PLL & Clock Generator System
When STA015 receives the input clock, as described in Section 2.1, and a valid layer III input bit stream,
the internal PLL locks, providing to the DSP Core the master clock (DCLK), and to the Audio Output Inter-
face the nominal frequencies of the incoming compressed bit stream. The STA015 PLL block diagram is
described in Figure 5.
The audio sample rates are obtained dividing the oversampling clock (OCLK) by software programmable
factors. The operation is done by STA015 embedded software and it is transparent to the user.
The STA015 PLL can drive directly most of the ommercial DACs families, providing an over sampling
clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers.
Figure 5. PLL and Clocks Generation System
2.3 STA015 Operational Modes
The device can be configured in 4 different operational modes. To select one specific mode a dedicated
CHIP_MODE registers is available. For proper operation the following steps must be issued to switch be-
tween different modes:
Hereby is a short description of each available mode
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– issue a software reset (SOFT_RESET register)
– select the desired mode (CHIP_MODE register)
– run the device (RUN register)
ADPCM Encoder
This mode can be used to encode the incoming bitstream with 4 different compression algorithms.
Moreover different sample frequencies and word size are supported. For a detailed escription of this
features refer to the related registers.
ADPCM Decoder
This mode can be used when an ADPCM compressed bitstream must be decoded. The input interface
handling and control flow is the same as in the MP3 Mode.
BYPASS mode
Using this mode it’s possible to use the embedded post-processing controls (volume and tone controls)
to process an incoming uncompressed stereo audio stream. In this configuration ADC input is the only
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