AD9849AKST Analog Devices Inc, AD9849AKST Datasheet
AD9849AKST
Specifications of AD9849AKST
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AD9849AKST Summary of contents
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FEATURES AD9848: 10-Bit, 20 MHz Version AD9849: 12-Bit, 30 MHz Version Correlated Double Sampler (CDS) – +10 dB Pixel Gain Amplifier ( PxGA 10-Bit Variable Gain Amplifier (VGA) 10-Bit 20 MHz A/D ...
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AD9848/AD9849 –SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE AD9848 AD9849 POWER SUPPLY VOLTAGE, AD9848 Analog (AVDD1 Digital1 (DVDD1) H1–H4 Digital2 (DVDD2) RG Digital3 (DVDD3) D0–D11 Digital4 (DVDD4) All Other Digital POWER SUPPLY VOLTAGE, AD9849 ...
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DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage ...
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AD9848/AD9849 AD9848–ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient* Max Input Range Before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (32) ...
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AD9849–ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient* Max Input Range Before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (32) Med ...
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AD9848/AD9849 TIMING SPECIFICATIONS Parameter MASTER CLOCK (CLI), AD9848 CLI Clock Period CLI High/Low Pulsewidth Delay From CLI to Internal Pixel Period Position MASTER CLOCK (CLI), AD9849 CLI Clock Period CLI High/Low Pulsewidth EXTERNAL MODE CLAMPING CLPDM Pulsewidth CLPOB Pulsewidth* SAMPLE ...
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... DVSS3 –0.3 DVSS4 –0.3 AVSS –0.3 DVSS4 –0.3 AVSS –0.3 AVSS –0.3 ORDERING GUIDE Temperature Model Range AD9848AKST –20°C to +85°C AD9849AKST –20°C to +85°C –7– AD9848/AD9849 Max Unit +3.9 V +3.9 V +5.5 V +3.9 V DVDD3 + 0.3 V DVDD4 + 0.3 V AVDD + 0.3 V DVDD4 + 0 ...
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AD9848/AD9849 (LSB PIN IDENTIFIER AD9848 DVSS3 6 TOP VIEW DVDD3 7 (Not to Scale ...
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EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD2 R AVSS2 Circuit 1. CCDIN (Pin 29) AVDD1 330 25k CLI 1.4V AVSS1 Circuit 2. CLI (Pin 23) DVDD4 DATA THREE- STATE DVSS4 Circuit 3. Data Outputs D0–D11 (Pins 1–5, 8–12, 47–48) REV. A AVSS2 Circuit ...
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AD9848/AD9849 —Typical Performance Characteristics 0.50 0.25 0 –0.25 –0.50 0 400 200 600 TPC 1. AD9848 Typical DNL 400 200 600 VGA GAIN CODE – LSB TPC 2. AD9848 Output Noise vs. VGA Gain ...
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SYSTEM OVERVIEW V-DRIVER V1–V4, VSG1–VSG8, SUBCK H1–H4, RG CCDIN AD9848/AD9849 CCD INTEGRATED AFE+TD SERIAL INTERFACE Figure 1a. Typical Application (Internal Mode) Figures 1a and 1b show the typical system application diagrams for the AD9848/AD9849. The CCD output is processed by ...
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AD9848/AD9849 SERIAL INTERFACE TIMING SDATA SCK NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. ...
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Accessing a Double-Wide Register There are many double-wide registers in the AD9848/AD9849, for example, oprmode, clpdmtog1_0, and clpdmscp3, and so on. These registers are configured into two consecutive 6-bit registers with the least significant six bits located in the lower ...
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AD9848/AD9849 Bit Address Content Width CLPDM # Bits 146 [5: [5: [5: [5: [ [5: [5: ...
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Bit Default Address Content Width Value CLPOB # Bits 146 [5: [5: [5: [5: [0] ...
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AD9848/AD9849 Bit Default Address Content Width Value HBLK # Bits 147 [5: [5: [5: ...
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Bit Default Address Content Width Value PBLK # Bits 146 [5: [5: [5: [5: [0] ...
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AD9848/AD9849 Bit Default Address Content Width Value AFE REGISTER BREAKDOWN oprmode [7:0] 8'h0 [1:0] 2'h0 2'h1 2'h2 2'h3 [2] [3] [4] [5] [6] [7] ctlmode [5:0] 6'h0 [2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 [3] [4] 1'h0 1'h1 ...
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POSITION P[0] CLI t CLIDLY 1 PIXEL PERIOD NOTES 1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL ...
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AD9848/AD9849 Table II. H1–H4, RG, SHP, SHD Timing Parameters Register Name Length Range POL 1b High/Low POSLOC 6b 0–47 Edge Location NEGLOC 6b 0–47 Edge Location DRV 3b 0–7 Current Steps Quadrant Edge Location (Decimal ...
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HD (2) CLPOB (1) CLPDM CLAMP PBLK NOTES PROGRAMMABLE SETTINGS: (1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) (2) FIRST TOGGLE POSITION (3) SECOND TOGGLE POSITION HD (2) (1) BLANK HBLK NOTES PROGRAMMABLE SETTINGS: (1) FIRST TOGGLE POSITION ...
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AD9848/AD9849 SEQUENCE CHANGE OF POSITION #0 SEQUENCE CHANGE OF POSITION #1 SEQUENCE CHANGE OF POSITION #2 SEQUENCE CHANGE OF POSITION # FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE ...
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POWER-UP PROCEDURE VDD (INPUT) CLI (INPUT) t PWR SERIAL WRITES VD (OUTPUT) HD (OUTPUT) H2/H4 DIGITAL H1/H3, RG OUTPUTS Recommended Power-Up Sequence When the AD9848 and AD9849 are powered up, the following sequence is recommended (refer to Figure 14 for ...
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AD9848/AD9849 DC RESTORE 1.5V SHP SHD 0.1 F CCDIN CDS INPUT OFFSET 0.1 F BYP1 0.1 F BYP 2 0.1 F BYP 3 FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE ...
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FLD VD HD PxGA GAIN REGISTER NOTES 1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE. 2. FLD RISING EDGE (START OF EVEN FIELD) WILL ...
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AD9848/AD9849 FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN ...
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PxGA The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to “multiplex” its gain value on a pixel-to-pixel basis (see Figure 17). This allows lower ...
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AD9848/AD9849 Variable Gain Amplifier The VGA stage provides a gain range dB, program- mable with 10-bit resolution through the serial digital interface. Combined with 4 dB from the PxGA stage, the total gain range for ...
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DIGITAL SUPPLY 0 DVSS3 DRIVER SUPPLY DVDD3 D10 (MSB) D11 12 DATA OUTPUTS H DRIVER SUPPLY RG DRIVER SUPPLY Figure 21. Recommend Circuit Configuration for External Mode Driving the CLI ...
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AD9848/AD9849 AD9848/AD9849 SIGNAL OUT CCD IMAGER H2 Figure 22b. CCD Connections (4 H-Clock) AD9848/AD9849 23 CLI Figure 23a. CLI Connection, DC-Coupled AD9848/AD9849 23 CLI 1nF Figure 23b. ...
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Timing Examples (continued) CCDIN INVALID PIXELS VERT SHIFT DUMMY SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY ...
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AD9848/AD9849 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 1/03—Data Sheet changed from REV REV. A. Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . ...