AD9849AKST Analog Devices Inc, AD9849AKST Datasheet - Page 20

• Manufacturer Part Number: AD9849AKST
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9849AKST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7/3V
• Operating Supply Voltage (typ): 3/3.3/5V
• Operating Supply Voltage (max): 3.6/5.5V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9848/AD9849
Register Name
POL
POSLOC
NEGLOC
DRV
Quadrant
I
II
III
IV
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9848/
AD9849 features on-chip output drivers for the RG and H1–H4
outputs. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver current can be adjusted for optimum
rise/fall time into a particular load by using the DRV registers.
The RG drive current is adjustable using the RGDRV register.
Each 3-bit DRV register is adjustable in 3.5 mA increments, with
the minimum setting of 0 equal to OFF or three-state, and the
maximum setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than l ns, which is significantly less than the typical rise time
driving the CCD load. This results in a H1/H2 crossover voltage
at approximately 50% of the output swing. The crossover voltage
is not programmable.
1 PIXEL PERIOD
Edge Location (Decimal)
0 to 11
12 to 23
24 to 35
36 to 47
H1/H3
H2/H4
6b
6b
3b
Length
1b
DOUT
CLI
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
P[0]
t
RISE
0–47 Edge Location
0–47 Edge Location
0–7 Current Steps
Range
High/Low
Table II. H1–H4, RG, SHP, SHD Timing Parameters
t
OD
Figure 7. H-Clock Inverse Phase Relationship
Figure 8. Digital Output Phase Adjustment
Table III. Precision Timing Edge Locations
FIXED CROSSOVER VOLTAGE
P[12]
t
PD
<<
t
RISE
Register Value (Decimal)
0 to 11
16 to 27
32 to 43
48 to 59
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
Negative Edge Location for H1, H3, and RG
Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)
Description
–20–
P[24]
Digital Data Outputs
The AD9848/AD9849 data output phase is programmable
using the DOUTPHASE register. Any edge from 0 to 47 may
be programmed, as shown in Figure 8.
HORIZONTAL CLAMPING AND BLANKING
The AD9848/AD9849’s horizontal clamping and blanking
pulses are fully programmable to suit a variety of applications.
As with the vertical timing generation, individual sequences are
defined for each signal and are then organized into multiple
regions during image readout. This allows the dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.
H1/H3
P[36]
t
PD
Register Value (Binary)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
P[48] = P[0]
H2/H4
REV. A