FIN212ACGFX Fairchild Semiconductor, FIN212ACGFX Datasheet
FIN212ACGFX
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FIN212ACGFX Summary of contents
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... Fairchild’s proprietary ultra-low power, low- <10 µA EMI technology. 2.5 to 3.6V 1.65 to 3.6V 14kV Applications 32-Terminal MLP 42-Ball USS-BGA Slider, Folder, & Clamshell Mobile Handsets FIN212ACMLX Printers FIN212ACGFX Security Cameras Related Resources For samples and questions, please contact: Interface@fairchildsemi.com. Internal Termination FIN212AC + + 2 - ...
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... N/C PLL1 PLL0 DP[12] 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 2. FIN212AC (Serializer DIRI=1) Pin Assignments (Top View) © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. ...
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... DP[12] N/C PWS1 PWS0 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 3. FIN212AC (Deserializer DIRI=0) Pin Assignments (Top View) © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 0 Deserializer 1 Serializer 0 Internal termination used 1 External termination required on CKSI & DSI See Table 2 Deserializer (DIRI=0) Control Pin. ...
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... L Inverted Non-Inverted [Typically for 20MHz to 40MHz signals] Non-Inverted Table 2: Deserializer (DIRI=0) Control Pin © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 Function CKREF STROBE Slow Frequencies 5MHz to 14MHz ≤ CKREF (Up to 14MHz) 4.7MHz to 13.3MHz ≤ CKREF (Up to 13.3MHz) 5MHz to 14MHz ≤ ...
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... PLL Note Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end of the higher speed PLL range. © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 DIRI=0 (Deserializer) High-Z ...
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... PWS0 A3 XTRM GND /RES Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package) Deserializer Configuration: ~2 – 3ns output edge rates (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 FIN212AC Deserializer VDD VDDS/A VDDS CKSO+ ...
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... Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package) Serializer Configuration: 20MHz to 40MHz Frequency Range (S1=0, S0=1) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 FIN212AC Serializer VDD ...
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... Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter LVCMOS I/O V Input High Voltage IH V Input Low Voltage IL © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 Parameter Serial I/O Pins to GND All Pins Parameter Test Conditions 8 Min. Max. ...
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... Current Dynamic Deserializer Power I DD_DES1 Supply Current Pin Capacitance Tables Symbol Parameter Capacitance of Input Only Signals; Parallel IO-DIFF Port Pins DP[1:10]; Differential I/O © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 (Continued) I =-2.0mA, S1=0,S0 =-0.4mA, S1=1,S0 =-1.0mA, S1=1,S0 =2.0mA, S1=0,S0 ...
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... DP[1:12] Data t RCOP 75% CKP 50% 25% t PDV t t RCOH RCOL Setup: DIRI= 0, CKSI and DS are valid signals. © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 Test Conditions S1=0, S0 S1=1, S0=0 CKREF STRB S1=1, S0=1 PLL1=0, PLL0=0 PLL1=0, PLL0=1 f ≠ f CKREF STRB ...
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... PHZ Deserializer Disable Time LOW to DPTri-State; DIRI=0, t DISDES DISDES DP Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid. t Serializer Disable Time LOW to CKP HIGH DISSER © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 (Continued) S1=0,S0=1 C =8pF S1=1,S0=0 L S1=1,S0=1 S1=0,S0=1 C =8pF ...
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... A, B, and C). MLP Shipping Reel Dimensions 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Dia A max Dia A Dim B Tape Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1 Min. ±0.1 ± ...
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... BGA Shipping Reel Dimensions 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Dia A max Dia A Dim B Tape Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2008 Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 (Continued Min. ±0.1 ± ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Figure 11. 42-Ball, Ball Grid Array (BGA) Package Operating Order Number Temperature Range FIN212ACGFX -30 to 70°C For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ ...
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... Fairchild Semiconductor Corporation FIN212AC • Rev. 1.1.0 16 www.fairchildsemi.com ...