FIN212ACGFX Fairchild Semiconductor, FIN212ACGFX Datasheet - Page 2

• Manufacturer Part Number: FIN212ACGFX
• Description: IC SER/DESER 12BIT 42USS-BGA
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN212ACGFX

• Function: Serializer/Deserializer
• Data Rate: 560Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 12
• Number Of Outputs: 12
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 42-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN212ACGFXTR

FIN212AC (Serializer DIRI=1) Pin Descriptions
Note:
1.
FIN212AC (Serializer DIRI=1) Pin Configurations
© 2008 Fairchild Semiconductor Corporation
FIN212AC • Rev. 1.1.0
Pin Name
DIRI
CTL_ADJ
S0
S1
PLL0
PLL1
CKREF
STROBE
DP[1:12]
CKSO+
CKSO-
DSO+
DSO-
CKSI+
CKSI-
CKP
/DIRO
VDDP
VDDS
VDDA
GND
N/C
G
A
B
C
D
E
F
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
0=GND; 1=VDDP
DP[10]
DP[12]
DP[4]
DP[6]
DP[8]
CKP
N/C
1
DP[11]
DP[2]
DP[5]
DP[7]
DP[9]
N/C
N/C
2
Description
Control to determine serializer or deserializer configuration.
Adjusts CTL drive to compensate for environmental conditions
and length.
Configure frequency range for the PLL.
Configure frequency range for the PLL.
Divide or adjust the serial frequency.
Divide or adjust the serial frequency.
LV-CMOS clock input and PLL reference.
LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge.
LV-CMOS parallel data input. (GND input if not used)
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
CTL Differential serial output data signals.
DSO+: Positive signal; DSO-: Negative signal.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
LV-CMOS word clock output or Pixel clock output.
LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI
signal of the deserializer where the interface needs to be turned around.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded.
No connect. (Do not connect to GND or VDD)
VDDP
DP[1]
DP[3]
PLL1
GND
GND
N/C
3
Figure 2. FIN212AC (Serializer DIRI=1) Pin Assignments (Top View)
CTL_ADJ
VDDS
VDDA
PLL0
GND
N/C
N/C
4
STROBE
CKSO+
CKSI+
DSO-
N/C
N/C
S1
5
CKREF
CKSO-
/DIRO
DSO+
CKSI-
DIRI
S0
6
VDDP
DP[4]
DP[5] 2
DP[6]
DP[7] 6
DP[8] 7
DP[9] 8
CKP 5
2
1
3
4
32-pin MLP, 5 x 5mm, .5mm pitch (Top View)
0 Deserializer
1 Serializer
0 Low drive (low power)
1 High drive (high power)
No connect unless in “clock pass-through” mode.
No connect unless in “clock pass-through” mode.
See Table 1 Serializer (DIRI=1) Control Pin.
See Table 1 Serializer (DIRI=1) Control Pin.
See Table 1 Serializer (DIRI=1) Control Pin.
See Table 1 Serializer (DIRI=1) Control Pin.
SERIALIZER
GND PAD
No connect if not used.
www.fairchildsemi.com
24
23
22
21
20
19
18
17
CKSO+
CKSO-
DSO+
DSO-
CKSI-
CKSI+
DIRI
VDDS