LMH0030VS/NOPB National Semiconductor, LMH0030VS/NOPB Datasheet - Page 11

• Manufacturer Part Number: LMH0030VS/NOPB
• Description: IC SERIALIZER VID DGTL 64-TQFP
• Manufacturer: National Semiconductor
• Series: LMH®r

Specifications of LMH0030VS/NOPB

• Function: Serializer
• Data Rate: 1.485Gbps
• Input Type: CMOS
• Output Type: CMOS
• Number Of Inputs: 8
• Number Of Outputs: 8
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD130EVK - BOARD EVALUATION LMH0030
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0030VS/NOPB; LMH0030VS

clocking it into the device on or before the falling edge of
ACLK. Observe the port input hold timing specification.
Example: Setup (without enabling) the TPG Mode via the AD
port using the 1125 line, 30 frame, 74.25MHz, interlaced com-
ponent (SMPTE 274M) color bars as test pattern. The TPG
may be enabled after setup using the Multi-function I/O port
or by the control registers.
ANCILLARY DATA FUNCTIONS
The LMH0030 can multiplex Ancillary Data into the serial
component video data stream. The ancillary data packet
structure, formatting and control words are given in standard
SMPTE 291M. The data may reside in portions of the hori-
zontal and vertical blanking intervals. The data can consist of
different types of message packets including audio data. The
LMH0030 supports ancillary data in the HANC and VANC ar-
eas of standard definition component video and in the chromi-
nance channel (C’r/C’b) only for high-definition operation. As
it applies to embedded (multiplexed) audio data, this function
follows the recommended practice for AES/EBU default Level
A data handling.
Figure 3 shows the sequence of clock, data and control sig-
nals for writing Ancillary Data to the port. In ancillary data
write mode, 10-bit ancillary data is written into the AD[9:0]
port and subsequently into the ancillary data FIFO. From the
FIFO, the ancillary data can be inserted into the ancillary data
areas in the serial video data stream. Ancillary data may be
written to the FIFO only when in the ancillary data mode. An-
cillary data cannot be read from the FIFO through the AD Port.
The process of loading ancillary data into the FIFO is done
during the active video portion of the video line. Occurrence
of the active video line interval is indicated by the H-bit in the
fourth word of the TRS sequence. The H-bit is available on I/
O Port bit-2.
FIGURE 2. Control Data Write Timing
11
1.
2.
3.
4.
5.
6.
The ancillary data write process begins by making the ANC/
CTRL input high and the RD/WR input low. Next, the data
words are presented to the port in sequence as specified in
SMPTE 291M beginning with the DID word. Data presented
to the port within the required setup and hold time parameters
will be written into the FIFO on the rising edge of ACLK. The
user has the option of including a checksum in the ANC input
data or of having the LMH0030 calculate and append the
checksum. The LMH0030 will append the Ancillary Data Flag
to each packet automatically before multiplexing with the
video data.
The process of writing ancillary data to the FIFO is effectively
a double-buffered write operation. Therefore, in order to prop-
erly write the last word of the data packet, the CRC, whether
supplied with the ANC data packet or internally generated, to
the FIFO, ACLK must be toggled two additional times after
the last data word is clocked into the port (or when the CRC
is being generated internally and appended). In the case
where multiple packets are being loaded to the FIFO, the ad-
ditional clocks are issued after the last word of the final packet
is received by the port.
Writing of ancillary data to the FIFO, packet handling and in-
sertion into the video data stream are controlled by a system
of masking and control bits in the control registers. These and
other ancillary data control functions such as CHKSUM AT-
TACH IN are explained in detail later in this data sheet.
Set ANC/CTRL to a logic-low.
Set RD/WR to a logic-low.
Present 00Dh to AD[9:0] as the Test 0 register address.
Toggle ACLK.
Present 327h to AD[9:0] as the register data.
Toggle ACLK.
20180310
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