LMH0030VS/NOPB National Semiconductor, LMH0030VS/NOPB Datasheet - Page 18

• Manufacturer Part Number: LMH0030VS/NOPB
• Description: IC SERIALIZER VID DGTL 64-TQFP
• Manufacturer: National Semiconductor
• Series: LMH®r

Specifications of LMH0030VS/NOPB

• Function: Serializer
• Data Rate: 1.485Gbps
• Input Type: CMOS
• Output Type: CMOS
• Number Of Inputs: 8
• Number Of Outputs: 8
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD130EVK - BOARD EVALUATION LMH0030
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0030VS/NOPB; LMH0030VS

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EDH REGISTERS 0, 1 AND 2 (Addresses 01h through 03h)
Updated EDH packets may be inserted into the serial output
data by setting the EDH Force bit in the control registers. The
EDH Force control bit causes the insertion of new EDH
checkwords and flags into the serial output regardless of the
previous condition of EDH checkwords and flags in the input
parallel data. This function may be used in situations where
video content has been editted thus making the previous EDH
information invalid. In the case of SMPTE 292M data, the
CRC check characters are recalculated and inserted auto-
matically regardless of the presence of CRC characters in the
parallel data. After the LMH0030 is reset, the initial state of
the CRC check characters is 00h.
The EDH Enable bit enables operation of the EDH generator
function.
The EDH ERROR (SD) bit when set indicates that EDH error
conditions are being reported in EDH ancillary data packets
present in the parallel input data. Details of the specific error
conditions contained in the EDH packets are reported via the
full field, active picture and ancillary flag error bits and the
specific flag bits in these registers.
The EDH flags F/F FLAGS[4:0] (full field), A/P FLAGS[4:0]
(active picture) and ANC FLAGS[4:0] (ancillary data) are de-
fined in SMPTE RP 165. The EDH flags are stored in the
control registers. The flags are updated automatically when
the EDH function is enabled and data is being received.
EDH 0
EDH 1
EDH 2
ANC 0
ANC 1
ANC 2
ANC 3
ANC 4
ANC 5
ANC 6
SWITCH POINT 0
SWITCH POINT 1
SWITCH POINT 2
SWITCH POINT 3
FORMAT 0
FORMAT 1
TEST 0
VIDEO INFO 0
I/O PIN 0 CONFIG
I/O PIN 1 CONFIG
I/O PIN 2 CONFIG
I/O PIN 3 CONFIG
I/O PIN 4 CONFIG
I/O PIN 5 CONFIG
I/O PIN 6 CONFIG
I/O PIN 7 CONFIG
TEST MODE 0
Register Name
TABLE 3. Control Register Addresses
Address
Decimal
23
24
10
25
26
11
12
13
14
15
16
17
18
19
20
21
22
85
1
2
3
4
5
6
7
8
9
Hexadecimal
Address
0C
0D
0A
1A
0B
0E
0F
01
02
03
04
05
06
07
08
17
18
09
19
10
11
12
13
14
15
16
55
18
The status of EDH flag errors in incoming SD parallel data are
reported in the ffFlagError, apFlagError and ancFlagError
bits. The ffFlagError, apFlagError and ancFlagError bits
are the logical-OR of the corresponding EDH and EDA flags
of the EDH checkwords.
ANC REGISTER 0 (Address 04h)
The V FIFO Depth[2:0] bits control the depth of the video
FIFO which follows the input data latches. The depth can be
set from 0 to 4 stages deep by writing the corresponding bi-
nary code into these bits. For example: to set the Video FIFO
depth at two registers, load 11010XXXXXb into the ANC 0
control register (where X represents the other functional bits
of this register). To retain other data previously stored in a
register, read the register’s contents and logically-OR this
with the new data. Then write the composite data back into
the register.
Flags for FIFO EMPTY, FIFO FULL and FIFO OVERRUN are
available in the configuration and control register set. These
flags can also be assigned as inputs and outputs on the multi-
function I/O port. The FIFO OVERRUN flag indicates that an
attempt to write data into a full FIFO has occurred.
The ANC Checksum Force bit, under certain conditions, en-
ables the overwriting of ancillary data checksums received in
the parallel ancillary data. Calculation and insertion of new
ancillary data checksums is controlled by the ANC Check-
sum Force bit. If a checksum error is detected (calculated
and received checksums do not match) and the ANC Check-
sum Force bit is set, a new checksum will be inserted in the
ancillary data replacing the previous one. If a checksum error
is detected and the ANC Checksum Force bit is not set, the
checksum mismatch is reported via the ANC Checksum Er-
ror bit.
Ancillary data checksums may be received in the incoming
parallel ancillary data. Alternatively they may be calculated
and inserted automatically by the LMH0030. The CHKSUM
ATTACH IN bit in the control registers when set to a logic-1
indicates that the checksum is to be supplied in the incoming
data. When the CHKSUM ATTACH IN bit is set, checksums
for incoming data are calculated and checked against re-
ceived checksums. Calculation and insertion of new ancillary
data checksum is controlled by the ANC Checksum Force
bit in the configuration and control registers. If a checksum
error is detected (calculated and received checksums do not
match) and the ANC Checksum Force bit is set, a new
checksum will be inserted in the ancillary data replacing the
previous one. If a checksum error is detected and the ANC
Checksum Force bit is not set, the checksum mismatch is
reported via the ANC CHECKSUM ERROR bit in the control
registers.
The ANC Checksum Error bit indicates that the received
ancillary data checksum did not agree with the LMH0030's
internally generated checksum. This bit is available as an
output on the multifunction I/O port.
ANC REGISTERS 1 THROUGH 4 (Address 05h through
08h)
Admission of ancillary data packets into the FIFO can be con-
trolled by the ANC MASK[15:0] and ANC ID[15:0] bits in the
control registers. The ANC ID[7:0] register can be set to a
valid 8-bit Data Identification (DID) code used for component
ancillary data packet identification as specified in SMPTE
291M. Similarly, theANC ID[15:8] register can be set to a
valid 8-bit Secondary Data Identification (SDID) or Data Block
Number (DBN) code. The ANC MASK[7:0] is an 8-bit word
that can be used to selectively control loading of packets with