LMH0030VS/NOPB National Semiconductor, LMH0030VS/NOPB Datasheet - Page 13

• Manufacturer Part Number: LMH0030VS/NOPB
• Description: IC SERIALIZER VID DGTL 64-TQFP
• Manufacturer: National Semiconductor
• Series: LMH®r

Specifications of LMH0030VS/NOPB

• Function: Serializer
• Data Rate: 1.485Gbps
• Input Type: CMOS
• Output Type: CMOS
• Number Of Inputs: 8
• Number Of Outputs: 8
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD130EVK - BOARD EVALUATION LMH0030
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0030VS/NOPB; LMH0030VS

line length, number of video lines in a frame, and so forth. This
is done so that information like line numbering can be cor-
rectly inserted. The PLL itself will have locked in 200 mi-
croseconds (HD rates) or less. However, resolution of all
raster parameters may take the majority of a frame.
SERIAL DATA OUTPUT DRIVER
The serial data outputs provide low-skew complimentary or
differential signals. The output buffer is a current-mode de-
sign and is intended to drive AC-coupled and terminated,
75Ω coaxial cables. The driver automatically adjusts its output
slew rate depending upon the data rate being processed.
Output levels are 800 mV
loads. The 75Ω resistors connected to the SDO outputs func-
tion both as drain-load and back-matching resistors. Series
back-matching resistors are not used with this output type.
The serial output level is controlled by the value of R
and R
The R
put signal to the required SMPTE nominal level. The
R
which is active during the transition times of the HD-rate out-
put signal. The value of R
The value of R
present at these pins is approximately +1.3Vdc. The transition
times of this output buffer design automatically adjust and are
different for the HD and SD data rate conditions. The output
buffer is quiescent when the device is in an out-of-lock con-
dition. The output will become active after the PLL is locked
and a valid format has been detected. Separate power feeds
are provided for the serial output driver: V
and 59; V
CAUTION: This output buffer is not designed or specified for
driving 50Ω or other impedance loads.
NOTE: The SMPTE return loss specification is highly depen-
dent on board design and can be challenging to meet with the
LMH0030's integrated cable driver. In order to meet the
SMPTE return loss specification, it is recommended to use an
external cable driver such as the LMH0002 HD/SD SDI cable
driver on the output of the LMH0030.
POWER SUPPLIES, POWER-ON-RESET AND RESET
INPUT
The LMH0030 requires two power supplies, 2.5V for the core
logic functions and 3.3V for the I/O functions. The supplies
must be applied to the device in proper sequence. The 3.3V
supply must be applied prior to or coincident with the 2.5V
supply. Application of the 2.5V supply must not precede the
3.3V supply. It is recommended that the 3.3V supply be con-
figured or designed so as to control application of the 2.5V
supply in order to satisfy this sequencing requirement.
The LMH0030 has an automatic, power-on-reset circuit. Re-
set initializes the device and clears TRS detection circuitry,
all latches, registers, counters and polynomial generators,
sets the EDH/CRC characters to 00h and disables the serial
output. Table 1 lists the initial conditions of the configuration
and control registers. An active-HIGH-true, manual reset in-
put is available at pin 64. The reset input has an internal pull-
down device and may be considered inactive when uncon-
nected.
Important: When power is first applied to the device or fol-
lowing a reset, the Ancillary and Control Data Port must be
initialized to receive data. This is done by toggling ACLK three
times.
REF
PRE resistor sets the value of a pre-emphasis current
REF
REF
PRE connected to pin 53 and pin 52, respectively.
LVL resistor sets the peak-to-peak level of the out-
DDSD
REF
, pin 51; and V
PRE is normally 4.75 KΩ, ±1%. The voltage
REF
P-P
DDLS
LVL is normally 4.75 KΩ, ±1%.
±10% into 75Ω AC-coupled
, pin 57.
SSSD
, pins 54, 55,
REF
LVL
13
TEST PATTERN GENERATOR (TPG) AND BUILT-IN
SELF-TEST (BIST)
The LMH0030 includes a built-in test pattern generator
(TPG). Four test pattern types are available for all data rates,
all HD and SD formats, NTSC and PAL standards, and 4x3
and 16x9 raster sizes. The test patterns are: flat-field black,
PLL pathological, equalizer (EQ) pathological and a 75%, 8-
color vertical bar pattern. The pathologicals follow the recom-
mendations of SMPTE RP 178-1996 regarding the test data
used. The color bar pattern has optional bandwidth limiting
coding in the chroma and luma data transitions between bars.
The VPG FILTER ENABLE bit in the VIDEO INFO 0 control
register enables the color bar filter function. The default con-
dition of VPG FILTER ENABLE is OFF.
The TPG also functions as a built-in self-test (BIST) which
can verify device functionality. The BIST function performs a
comprehensive go/no-go test of the device. The test may be
run using any of the HD color bar test patterns or one of two
SD test patterns, either a 270 Mbps NTSC full-field color bar
or a PAL PLL pathological, as the test data pattern. Data is
supplied internally in the input data register, processed
through the device and tested for errors using either the EDH
system for SD or the CRC system for HD. A go/no-go indica-
tion is logged in the Pass/Fail bit of the TEST 0 control
register set. This bit may be assigned as an output on the
multifunction I/O port.
TPG and BIST operation is initiated by loading the code for
the desired test pattern into the Test Pattern Select [5:0] bits
of the TEST 0 register. Table 5 gives the available test pat-
terns and codes. (Recall also the requirement to initialize the
ancillary data port control logic by clocking ACLK at least
three (3) complete cycles before attempting to load the first
register address). In the default power-on state, TPG En-
able appears as bit 7 on the multi-function I/O port. The TPG
is run by applying the appropriate frequency at the VCLK in-
put for the format and rate selected and then setting the TPG
Enable input on the multi-function I/O port, or by setting the
TPG Enable bit in the TEST 0 register.
Important: If the TPG Enable input of the I/O port is in its
default mapping and is not being used to enable the TPG
mode, attempting to enable TPG operation by setting bit 6 of
the TEST 0 register will not cause the TPG to operate. This
is because the low logic level at the I/O port input pulldown
overrides the high level being written to the register. The result
is the TPG does not run.
The Pass/Fail bit in the TEST 0 control register indicates the
test status. If no errors have been detected, this bit will be set
to logic-1 approximately 2 field intervals after TPG Enable is
set. If errors have been detected in the internal circuitry of the
LMH0030, Pass/Fail will remain reset to a logic-0. The TPG
or BIST is halted by resetting TPG Enable. The serial output
data is present at the SDO outputs during TPG or BIST op-
eration.
Caution ! When attempting to use the TPG or BIST immedi-
ately after applying power or resetting the device, the TPG
defaults to the 270 Mbps SD rate and expects a V
frequency of 27MHz as input. This is because the code for the
test pattern in the TEST 0 register is set to 00h (525 line, 30
frame, 27MHz, NTSC 4x3 reference black). Attempting to ap-
ply a V
ing to the setting in the TEST 0 register, may result in the PLL
locking up while attempting to slew to its maximum possible
frequency. This situation is not recoverable by the use of the
device RESET input. To recover from this condition, power
must be removed and re-applied to the device. Proper con-
ditioning of the V
CLK
frequency higher than the device expects, accord-
CLK
input, which does not have an internal
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CLK
clock