FIN24ACMLX Fairchild Semiconductor, FIN24ACMLX Datasheet - Page 10

• Manufacturer Part Number: FIN24ACMLX
• Description: IC SERIALIZER/DESERIALZR 40MLP
• Manufacturer: Fairchild Semiconductor
• Series: SerDes™r

Specifications of FIN24ACMLX

• Function: Serializer/Deserializer
• Data Rate: 520Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 20
• Number Of Outputs: 20
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -30°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

© 2005 Fairchild Semiconductor Corporation
FIN24AC Rev. 1.0.3
PLL Circuitry
The CKREF input signal is used to provide a reference to
the PLL. The PLL generates internal timing signals capa-
ble of transferring data at 26 times the incoming CKREF
signal. The output of the PLL is a bit clock that is used to
serialize the data. The bit clock is also sent source syn-
chronously with the serial data stream.
Figure 10. Bi-Directional Differential I/O Circuitry
Deserializer
Serializer
From
To
Control
From
+
–
+
–
Gated
Termination
(DS Pins Only)
DS+
DS-
10
There are two ways to disable the PLL: by entering the
Mode 0 state (S1 = S2 = 0) or by detecting a LOW on
both the S1 and S2 signals. When any of the other
modes are entered by asserting either S1 or S2 HIGH
and by providing a CKREF signal. The PLL powers up
and goes through a lock sequence. Wait the specified
number of clock cycles prior to capturing valid data into
the parallel port. When the µSerDes chipset transitions
from a power-down state (S1, S2 = 0, 0) to a powered
state (example S1, S2 = 1, 1), CKP on the deserializer
transitions LOW for a short duration, then returns HIGH.
Following this, the signal level of the deserializer at CKP
corresponds to the serializer signal levels.
An alternate way of powering down the PLL is by stop-
ping the CKREF signal either HIGH or LOW. Internal cir-
cuitry detects the lack of transitions and shuts the PLL
and serial I/O down. Internal references,however, are not
disabled, allowing the PLL to power-up and re-lock in a
lesser number of clock cycles than when exiting Mode 0.
When a transition is seen on the CKREF signal, the PLL
is reactivated.
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