PCA9544APW,112 NXP Semiconductors, PCA9544APW,112 Datasheet - Page 6

• Manufacturer Part Number: PCA9544APW,112
• Description: IC I2C MUX 4CH BI-DIR 20-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9544APW,112

• Package / Case: 20-TSSOP
• Applications: 4-Channel I²C Multiplexer
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: PCA
• Number Of Lines (input / Output): 8.0 / 10.0
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 10.0
• Power Dissipation: 400 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1045-5; 935275806112; PCA9544APW

NXP Semiconductors
6. Functional description
PCA9544A_4
Product data sheet
6.2.1 Control register definition
6.1 Device addressing
6.2 Control register
Refer to
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9544A is shown in
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9544A which will be stored in the Control register. If multiple bytes are
received by the PCA9544A, it will save the last byte received. This register can be written
and read via the I
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9544A has been addressed. The 3 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, it will become active after a STOP condition has been placed on the I
This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of connection.
Fig 5.
Fig 6.
Figure 1 “Block
Slave address
Control register
2
C-bus.
Rev. 04 — 15 June 2009
bit
diagram”.
INT3 INT2 INT1 INT0
7
1
interrupt bits
(read only)
6
1
fixed
4-channel I
5
1
4
0
A2
X
3
selectable
hardware
enable bit
2
A1
C-bus multiplexer with interrupt logic
B2
channel selection bits
2
A0 R/W
002aab189
(read/write)
Figure
B1
1
002aae297
B0
0
5. To conserve power, no
PCA9544A
© NXP B.V. 2009. All rights reserved.
2
C-bus.
6 of 26