PCA9544APW,112 NXP Semiconductors, PCA9544APW,112 Datasheet - Page 7

• Manufacturer Part Number: PCA9544APW,112
• Description: IC I2C MUX 4CH BI-DIR 20-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9544APW,112

• Package / Case: 20-TSSOP
• Applications: 4-Channel I²C Multiplexer
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: PCA
• Number Of Lines (input / Output): 8.0 / 10.0
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 10.0
• Power Dissipation: 400 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1045-5; 935275806112; PCA9544APW

NXP Semiconductors
PCA9544A_4
Product data sheet
6.3 Interrupt handling
Table 4.
The PCA9544A provides 4 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9544A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte. Bits 7:4 of the control byte
correspond to channel 3 to channel 0 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 2, the state of the interrupt
inputs is loaded into the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of the control register to
be set on the read. The master can then address the PCA9544A and read the contents of
the control byte to determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544A to select this channel, and locate the
device generating the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to V
Table 5.
Remark: Several interrupts can be active at the same time. For example: INT3 = 0,
INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and
channel 3, and there is an interrupt on channel 1 and on channel 2.
INT3
X
X
X
X
X
0
INT3
X
X
X
0
1
INT2
X
X
X
X
X
0
INT2
X
X
X
0
1
Control register: Write—channel selection; Read—channel status
Control register read — interrupt
INT1
X
X
X
X
X
0
INT1
X
X
X
0
1
Rev. 04 — 15 June 2009
INT0
X
X
X
X
0
0
INT0
X
X
X
0
1
D3
X
X
X
X
X
0
D3
X
X
X
X
4-channel I
B2
0
1
1
1
1
0
B2
X
X
X
X
B1
X
0
0
1
1
0
B1
2
X
X
X
X
C-bus multiplexer with interrupt logic
DD
B0
x
0
1
0
1
0
through a pull-up resistor.
B0
X
X
X
X
Command
no channel selected
channel 0 enabled
channel 1 enabled
channel 2 enabled
channel 3 enabled
no channel selected;
power-up default state
Command
no interrupt on channel 0
interrupt on channel 0
no interrupt on channel 1
interrupt on channel 1
no interrupt on channel 2
interrupt on channel 2
no interrupt on channel 3
interrupt on channel 3
PCA9544A
© NXP B.V. 2009. All rights reserved.
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