KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 140
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 140 of 190
- Download datasheet (6Mb)
Table 10
Parameter
Class F Pads, CMOS Mode (
Input low voltage
Class F pins
Input high voltage
Class F pins
Input hysteresis
Class F pins
Input leakage
current Class F
pins
Output low voltage
6)
Output high
voltage
Class D Pads
See ADC Characteristics
1) Not subject to production test, verified by design / characterization.
2) Only one of these parameters is tested, the other is verified by design characterization
3) Maximum resistance of the driver
4) Function verified by design, value verified by design characterization.
5)
6) The following constraint applies to an LVDS pair used in CMOS mode: only one pin of a pair should be used
Data Sheet
25 / 20 Ω for strong driver mode,
200 / 150 Ω for medium driver mode,
600 / 400 Ω for weak driver mode,
verified by design / characterization.
Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce.
It cannot be guaranteed that it suppresses switching due to external system noise.
V
as output, the other should be used as input, or both pins should be used as inputs. Using both pins as outputs
is not recommended because of the higher crosstalk between them.
DDEBU
2) 6)
= 2.5 V ± 5%. For
Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)
Symbol
V
V
HYSF
I
V
V
OZF
ILF
IHF
OLF
OHF
V
DDEBU
SR
SR
CC
CC
CC
= 3.3 ± 5% see class A2 pads.
I
R
OH / L
I
V
DSON
Min.
-0.3
0.60 ×
V
0.05 ×
V
–
–
2.4
V
0.4
–
OH / L
DDP
DDP
DDP
DDP
I
OH / L
< 2 mA,
, defined for P_MOS / N_MOS transistor separately:
< 100 uA,
= 3.13 to 3.47 V = 3.3V ± 5%)
-
< 400 uA,
Values
–
–
–
–
–
–
–
–
Typ. Max.
136
0.36 ×
V
V
0.3 or
max.
3.6
–
±3000
±6000
0.4
–
–
–
DDP
DDP
+
Unit Note / Test Condition
V
V
V
nA
V
V
V
–
–
Whatever is lower
((
((
Otherwise
I
I
I
–
OL
OH
OH
V
V
DDP
DDP
Electrical Parameters
= 2 mA
= -2 mA
= -1.4 mA
/2)-1) <
/2)+1)
2)
<
V1.1, 2009-04
V
IN
TC1797
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