IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet - Page 18

• Manufacturer Part Number: IDT82V3002APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3002APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

4
MANCE
their corresponding definitions.
4.1
measured at its output. It is measured by applying a reference signal
with no jitter to the input of the device, and measuring its output jitter.
Intrinsic jitter may also be measured when the device is in a non-
synchronizing mode, such as free running or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various
band limiting filters depending on the applicable standards. In the
IDT82V3002A, the intrinsic Jitter is limited to less than 0.02 UI on the
2.048 MHz and 1.544 MHz clocks.
4.2
properly (i.e., remain in lock and or regain lock in the presence of large
jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and jitter frequency depends on
the applicable standards.
4.3
the output of a device for a given amount of jitter at the input of the
device. Input jitter is applied at various amplitudes and frequencies, and
output jitter is measured with various filters depending on the applicable
standards.
attenuation. This includes the internal 2.1 Hz low pass loop filter and the
phase slope limiter. The phase slope limiter limits the output phase slope
to 5 ns/125 µs. Therefore, if the input signal exceeds this rate, such as
for very large amplitude low frequency input jitter, the maximum output
phase slope will be limited (i.e., attenuated) to 5 ns/125 µs.
frequencies for a total of 42 possible jitter transfer functions. Since all
outputs are derived from the same signal, the jitter transfer values for
three cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to
2.048 MHz can be applied to all outputs.
equal to 1 UI at 2.048 MHz, which is 488 ns. Consequently, a transfer
value using different input and output frequencies must be calculated in
common units (e.g., seconds).
all combinations of inputs and outputs based on the three jitter transfer
functions provided. Note that the resulting jitter transfer functions for all
combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and outputs (8
kHz, 1.544 MHz, 3.088 MHz, 6.312 MHz, 2.048 MHz, 4.096 MHz, 8.192
MHz, 16.384 MHz, 32.768 MHz) for a given input signal (jitter frequency
and jitter amplitude) are the same.
be lower for small input jitter signals than for large ones. Consequently,
accurate jitter transfer function measurements are usually made with
MEASURES OF PERFORMANCE
IDT82V3002A
The following are some synchronizer performance indicators and
Intrinsic jitter is the jitter produced by the synchronizing circuit and is
Jitter tolerance is a measure of the ability of a DPLL to operate
Jitter transfer or jitter attenuation refers to the magnitude of jitter at
For the IDT82V3002A, two internal elements determine the jitter
The IDT82V3002A has fourteen outputs with three possible input
It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not
Using the above method, the jitter attenuation can be calculated for
Since intrinsic jitter is always present, jitter attenuation will appear to
MEASURES
INTRINSIC JITTER
JITTER TOLERANCE
JITTER TRANSFER
OF
PERFOR-
18
large input jitter signals (e.g., 75% of the specified maximum jitter
tolerance).
4.4
clock signal when it is not locked to an external reference, but is
operating in a free running mode. For the IDT82V3002A, the Freerun
accuracy is equal to the Master Clock (OSCi) accuracy.
4.5
clock signal, when it is not locked to an external reference signal, but is
operating using storage techniques. For the IDT82V3002A, the storage
value is determined while the device is in Normal Mode and locked to an
external reference signal.
does not affect Holdover accuracy, but the change in OSCi accuracy
while in Holdover Mode does.
4.6
over which the synchronizer must be able to pull into synchronization.
The IDT82V3002A capture range is equal to ±230 ppm minus the
accuracy of the master clock (OSCi). For example, a 32 ppm master
clock results in a capture range of 198 ppm.
should be able to reject references that are off the nominal frequency by
more than ±12 ppm. The IDT82V3002A provides one pin, MON_out, to
indicate whether the primary reference are within ±12 ppm of the
nominal frequency.
4.7
be able to maintain synchronization. The lock range is equal to the
capture range for the IDT82V3002A.
4.8
which a given signal changes phase with respect to an ideal signal. The
given signal is typically the output signal. The ideal signal is of constant
frequency and is nominally equal to the value of the final output signal or
final input signal.
4.9
timing signal.
4.10
signal and an ideal timing signal within a particular observation period.
Frequency accuracy is defined as the absolute tolerance of an output
Holdover accuracy is defined as the absolute tolerance of an output
The absolute Master Clock (OSCi) accuracy of the IDT82V3002A
Also referred to as pull-in range. This is the input frequency range
The Telcordia GR-1244-CORE standard, recommends that the DPLL
This is the input frequency range over which the synchronizer must
Phase slope is measured in seconds per second and is the rate at
TIE is the time delay between a given timing signal and an ideal
MTIE is the maximum peak to peak delay between a given timing
FREQUENCY ACCURACY
HOLDOVER ACCURACY
CAPTURE RANGE
LOCK RANGE
PHASE SLOPE
TIME INTERVAL ERROR (TIE)
MAXIMUM TIME INTERVAL ERROR (MTIE)
WAN PLL WITH DUAL REFERENCE INPUT
October 15, 2008