IDT82V3002APV IDT, Integrated Device Technology Inc, IDT82V3002APV Datasheet - Page 19

• Manufacturer Part Number: IDT82V3002APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3002APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

4.11
signal and an ideal timing signal at the end of a particular observation
period. Usually, the given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the output of the
synchronizer after a signal disturbance due to a mode change. The
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns/125 µs. This meets AT&T TR62411 maximum phase
slope requirement of 7.6 ns/125 µs and Telcordia GR-1244-CORE (81
ns/1.326 ms).
4.12
MEASURES OF PERFORMANCE
IDT82V3002A
Phase continuity is the phase difference between a given timing
In the case of the IDT82V3002A, the output signal phase continuity is
This is the time it takes the synchronizer to phase lock to the input
PHASE CONTINUITY
PHASE LOCK TIME
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signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
factors, which include:
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3002A
loop filter and limiter were optimized to meet the AT&T TR62411 jitter
transfer and phase slope requirements. Consequently, phase lock time,
which is not a standards requirement, may be longer than in other
applications. See
the DPLL to lock to an incoming reference within approximately 500 ms
when set high.
Lock time is very difficult to determine because it is affected by many
i) Initial input to output phase difference
ii) Initial input to output frequency difference
iii) Synchronizer loop filter
iv) Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
The IDT82V3002A provides a fast lock pin (FLOCK), which enables
Table - 8
WAN PLL WITH DUAL REFERENCE INPUT
for Maximum Phase Lock Time.
October 15, 2008