AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 138

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

31-16
15-0
CSR15: Mode
This register’s fields are loaded during the Am79C973/
Am79C975 controller initialization routine with the cor-
responding Initialization Block values, or when a direct
register write has been performed on this register.
Bit
31-16
15
14
138
RES
PADR[47:32]Physical
Name
RES
PROM
DRCVBC
zeros and read as undefined.
PADR[47:32].The
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
PROM = 1, all incoming receive
frames are accepted.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
When
Am79C973/Am79C975 controller
from receiving broadcast mes-
sages. Used for protocols that do
not support broadcast address-
ing, except as a function of multi-
cast. DRCVBC is cleared by
activation
S_RESET (broadcast messages
will be received) and is unaffect-
ed by STOP.
Reserved locations. Written as
This register can also be loaded
Description
Reserved locations. Written as
Promiscuous
Disable
set,
Receive
Address
of
read
Mode.
disables
H_RESET
contents
P R E L I M I N A R Y
Broadcast.
command
Am79C973/Am79C975
Register,
When
the
or
of
13
12-9
8-7 PORTSEL[1:0] Port Select bits allow for software
6
5
4
DRCVPA
RES
INTL
DRTY
FCOLL
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the Am79C973/Am79C975
controller
Frames addressed to the nodes
individual physical address will
not be recognized.
Reserved locations. Written as
zeros and read as undefined.
controlled selection of the net-
work medium. The only legal val-
ues for this field is 11.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Cleared by H_RESET or
S_RESET and is unaffected by
STOP.
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
Disable Retry. When DRTY is set
to 1, the Am79C973/Am79C975
controller will attempt only one
transmission. In this mode, the
device will not protect the first 64
bytes of frame data in the Trans-
mit FIFO from being overwritten,
because automatic retransmis-
sion will not be necessary. When
DRTY is set to 0, the Am79C973/
Am79C975 controller will attempt
16 transmissions before signal-
ing a retry error.
Force Collision. This bit allows
the collision logic to be tested.
The Am79C973/Am79C975 con-
will
be
disabled.