AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 206

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

RMD0
Bit
31-0
RMD1
Bit
31
30
29
206
CRDA+0Ch
CRDA+0Ch
CRDA+00h
CRDA+04h OWN ERR
CRDA+08h RES
CRDA+00h
CRDA+04h
CRDA+08h
Address
Address
RBADR
OWN
ERR
FRAM
Name
Name
OWN
31
31
30
Receive Buffer address. This field
contains the address of the re-
ceive buffer that is associated
with this descriptor.
This bit indicates whether the de-
scriptor entry is owned by the
host (OWN = 0) or by the
Am79C973/Am79C975 controller
(OWN = 1). The Am79C973/
Am79C975 controller clears the
OWN bit after filling the buffer that
the descriptor points to. The host
sets the OWN bit after emptying
the buffer.
ERR is the OR of FRAM, OFLO,
CRC, BUFF, or BPE. ERR is set
by the Am79C973/Am79C975
controller and cleared by the
host.
Framing error indicates that the
incoming frame contains a non-
integer multiple of eight bits and
Once the Am79C973/Am79C975
controller or host has relin-
quished ownership of a buffer, it
must not change any field in the
descriptor entry.
Description
Description
ERR
30
FRA
29
M
FRAM
29
OFL
28
O
Table 59. Receive Descriptor (SWSTYLE = 2)
Table 60. Receive Descriptor (SWSTYLE = 3)
OFLO
CRC
27
28
RES
P R E L I M I N A R Y
BUF
26
Am79C973/Am79C975
F
CRC
27
USER SPACE
STP ENP BPE
25
RFRTAG[14:0]
BUFF
26
USER SPACE
RBADR[31:0]
24
RBADR[31:0]
28
27
26
STP
25
23
OFLO
CRC
BUFF
PAM
22
ENP
24
LAFM
21
RES
BPE
23
CRC indicates that the receiver
Buffer error is set any time the
there was an FCS error. If there
was no FCS error on the incom-
ing frame, then FRAM will not be
set even if there was a non-
integer multiple of eight bits in the
frame. FRAM is not valid in inter-
nal loopback mode. FRAM is val-
id only when ENP is set and
OFLO is not. FRAM is set by the
Am79C973/Am79C975 controller
and cleared by the host.
Overflow error indicates that the
receiver has lost all or part of the
incoming frame, due to an inabili-
ty to move data from the receive
FIFO into a memory buffer before
the internal FIFO overflowed.
OFLO is set by the Am79C973/
Am79C975
cleared by the host.
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by the
Am79C973/Am79C975 controller
and cleared by the host. CRC will
also be set when Am79C973/
Am79C975 receives an RX_ER
indication from the external PHY
through the MII.
Am79C973/Am79C975 controller
does not own the next buffer
BAM
20
22-16
RES
RES
19-16
RES
15-12
controller
0000
1111
15-12
1111
0000
MCNT
BCNT
MCNT
BCNT
11-0
11-0
and