AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 37

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

pins carry the transmit output data and are connected
to the transmit side of the magnetics module.
RX+, RX-
Serial Receive Data
MLT-3/PECL
These pins are the 10BASE-T/100BASE-X port differ-
ential receiver pairs. They receive MLT-3 data and are
connected to the receive side of the magnetics module
in 100BASE-TX operation. They receive PECL NRZI
data from an exter nal fiber optic transceiver in
100BASE-FX application. For 10BASE-T, these pins
accept the receive input data from the magnetics mod-
ule.
SDI+, SDI-
Signal Detect
These pins control the selection between PECL and
MLT-3 data for the TX± and RX± pins. For 100BASE-
TX or 10BASE-T, both of these pins may be tied to
ground or left floating. This enables transmission and
reception of MLT-3 or 10BASE-T signals at the TX± and
RX± pins. For 100BASE-FX, these pins are biased at
PECL levels. They are connected to the SDI pin from
the optical transceiver module to indicate whether the
received signal is above the required threshold. If sig-
nal detect is not available, these pins should be tied to
a PECL logical 1 (SDI+ = PECL 1, SDI- = PECL 0). See
Table 2.
IREF
Internal Current Reference
This pin serves as a current reference for the integrated
10/100 PHY. It must be connected to ground via a
12 k resistor (1%).
Clock Interface
XTAL1
Crystal Input
The internal clock generator uses a 25-MHz (50 ppm-
100 ppm) crystal that is attached to the XTAL1 and
XTAL2 pins. XTAL1 may alternatively be driven using
an external 25 MHz (50 ppm - 100 ppm) CMOS-level
clock signal when XTAL2 is left floating. The XTAL1 pin
is not 5 V tolerant and must only be driven by a 3.3 V
clock source.
Table 2. SDI± Settings for Transceiver Operation
TTL HIGH
TTL LOW
(<0.8 V)
(>2.0 V)
SDI+
TTL HIGH
TTL LOW
(<0.8 V)
(>2.0 V)
SDI-
MLT-3/10BASE-T
PECL Mode
Port Mode
Mode
P R E L I M I N A R Y
Am79C973/Am79C975
Input
Input
Input
Input
XTAL2
Crystal Output
The internal clock generator uses a 25 MHz (50 ppm -
100 ppm) crystal that is attached to the pins XTAL1 and
XTAL2. XTAL1 may alternatively be driven using an ex-
ternal 25 MHz (50 ppm - 100 ppm) CMOS-level clock
signal when XTAL2 is left floating.
XCLK/XTAL
External Clock/Crystal Select
When HIGH, an External Clock Source is selected by-
passing the Crystal circuit. When LOW, a Crystal is
used instead. The following table illustrates how this pin
works.
Serial Management Interface (SMI)
(Am79C975 only)
MCLOCK
SMI Clock
MCLOCK is the clock pin of the serial management in-
terface. MCLOCK is typically driven by an external I
SMBus master. The Am79C975 controller will drive the
clock line low in order to insert wait states before it
starts sending out data in response to a read. The fre-
quency of the clock signal can vary between 10 kHz
and 100 kHz, and it can change from cycle to cycle.
Note: MCLOCK is also capable of running at a fre-
quency as high as 2.5 MHz to allow for shorter produc-
tion test time.
MDATA
SMI Data
MDATA is the data pin of the serial management inter-
face. MDATA can be driven by an external I
master or by the Am79C975 controller. The interface
protocol defines exactly at what time the Am79C975
controller has to listen to the MDATA pin and at what
time the controller must drive the pin.
MIRQ
SMI Interrupt
MIRQ is an asynchronous attention signal that the
Am79C975 controller provides to indicate that a man-
agement frame has been transmitted or received. The
assertion of the MIRQ signal can be controlled by a glo-
bal mask bit (MIRQEN) or individual mask bits
XATL1
XTAL1
Input Pin
Don’t Care
Output
XTAL2
Pin
XCLK/XTAL
0
1
Clock Source
External CLK
Input/Output
Input/Output
Oscillator/
Crystal
Source
2
C/SMBus
Output
Output
Input
2
37
C/