AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 179

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

BCR22: PCI Latency Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-8
MAX_LAT
SWSTYLE
Name
All Other
[7:0]
00h
01h
02h
03h
Reserved locations. Written as
zeros and read as undefined.
Maximum Latency. Specifies the
maximum arbitration latency the
Am79C973/Am79C975 controller
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated
Am79C975 controller. This action
is required, since the 16-bit soft-
ware structures specified by the
SSIZE32 = 0 setting will yield
only 24 bits of address for
Am79C973/Am79C975 controller
bus master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to
controller and the host system
will supply a full 32 bits for each
address pointer that is needed by
the Am79C973/Am79C975 con-
troller for performing master ac-
cesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
Description
the
by
Am79C973/Am79C975
PCnet-ISA
PCnet-PCI
PCnet-PCI
Reserved
controller
controller
controller
LANCE/
Name
Style
RES
the
Am79C973/
P R E L I M I N A R Y
Table 33. Software Styles
Am79C973/Am79C975
Undefined
SSIZE32
0
1
1
1
7-0
16-bit software
structures, non-burst or
burst access
RES
32-bit software
structures, non-burst or
burst access
32-bit software
structures, non-burst or
burst access
Undefined
SWSTYLE
Initialization Block
Entries
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C973/Am79C975
ler. The Software Style selection
will affect the interpretation of a
few bits within the CSR space,
the order of the descriptor entries
and the width of the descriptors
and initialization block entries.
All Am79C973/Am79C975 con-
troller CSR bits and all descriptor,
buffer, and initialization block en-
tries not cited in the Table 33 are
unaffected by the Software Style
selection and are, therefore, al-
ways fully functional as specified
in the CSR and BCR sections.
Read/Write accessible only when
either the STOP or the SPND bit
is set. The SWSTYLE register will
contain the value 00h following
H_RESET and will be unaffected
by S_RESET or STOP.
can sustain without causing prob-
lems to the network activity. The
register value specifies the time
in units of 1/4 microseconds.
MAX_LAT is aliased to the PCI
configuration
MAX_LAT (offset 3Fh). The host
will use the value in the register to
determine the setting of the
Am79C973/Am79C975 Latency
Timer register.
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst or burst access
Undefined
Descriptor Ring Entries
space
control-
register
179