S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 242

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

S1D13705F00A APPLICATION NOTES
(X27A-G-012-01)
IT8368E
PR31500/PR31700
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
LHA[16:13]/
MFIO[3:0]
/CARDxWAIT
Note: See Section on page 29 and Section on page 30 for Generic #1 pin descriptions.
The “Generic #1” host interface control signals of the S1D13705 are asynchronous with respect to
the S1D13705 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
DCLKOUT
HD[23:16]
HD[31:24]
HA[12:0]
ENDIAN
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 6-2 S1D13705 to PR31500/PR31700 Connection Using an IT8368E
V
DD
Clock divider
6: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
pull-up
EPSON
...or...
Oscillator
System RESET
+3.3V
See text
RESET#
AB[12:0]
AB[16:13]
DB[7:0]
DB[15:8]
WAIT#
BS#
WE1#
WE0#
RD/WR#
RD#
CS#
IO V
CLKI
BCLK
S1D13705
DD
, CORE V
5-41
DD