DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 13

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

3 FEATURE DETAILS
The following sections describe the features provided by the DS3171 (single), DS3172 (dual), DS3173 (triple), and
DS3174 (quad) single-chip transceivers (framers and LIUs, SCTs).
3.1 Global Features
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3.2 Receive DS3/E3 LIU Features
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3.3 Receive DS3/E3 Framer Features
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3.4 Transmit DS3/E3 Formatter Features
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Supports the following transmission protocols:
Optional transmit loop timed clock(s) mode using the associated port’s receive clock(s)
Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
Requires only a single reference clock for all three LIU data rates using internal CLAD
The LIU can be powered down and bypassed for direct logic IO to/from line circuits.
Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
Clock, data and control signals can be inverted for a direct interface to many other devices
Detection of loss of transmit clock and loss of receive clock
Automatic one-second, external or manual update of performance monitoring counters
Each port can be placed into a low-power standby mode when not being used
Framing and line code error insertion available
AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
Loss-of-lock PLL status indication
Interfaces directly to a DSX monitor signal (20 dB flat loss) using built-in pre-amp
Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Per-channel power-down control
Frame synchronization for M23 or C-bit Parity DS3, or G.751 E3 or G.832 E3
B3ZS/HDB3/AMI decoding
Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeros occurrences
(EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
errors, and far end block errors (FEBE)
Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of
frame alignment (COFA), receipt of B3ZS/HDB3 codewords, DS3 application ID bit, DS3 M23/C-bit format
mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
FEAC port for DS3 FEAC channel
16-byte Trail Trace Buffer port for G.832 trail access point identifier
DS3 M23 C bits and stuff bits configurable as payload or overhead, stored in registers for software inspection
Most framing overhead fields presented on the receive overhead port
Insertion of framing overhead for M23 or C-bit parity DS3, or G.751 E3 or G.832 E3
B3ZS/HDB3 encoding
Generation of RDI, AIS, and DS3 idle signal
Automatic or manual insertion of bipolar violations (BPVs), excessive zeros (EXZ) occurrences, F-bit errors, M-
bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE)
HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
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C-bit DS3
M23 DS3
G.751 E3
G.832 E3
Clear-channel serial data at line rates up to 52 Mbits/s
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