DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 48

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

9 INITIALIZATION AND CONFIGURATION
STEP 1: Check Device ID Code:
Before any testing can be done, device ID code, which is stored in GL.IDR, should be checked against device ID
codes shown below to ensure correct device is being used.
Current device ID codes are:
STEP 2: Initialize the Device.
Before configuring for operation, make sure the device is in a known condition with all registers set to their default
value by initiating a Global Reset (see Section 10.3). A Global Reset can be initiated via the RST pin or by the
Global Reset bit (GL.CR1.RST). A Port Reset is not necessary since the global reset includes a reset of all ports to
their default values.
STEP 3: Clear the Reset.
It is necessary to clear the RST bit to begin normal operation.
After clearing the RST bit, the device is configured for default mode.
Default mode:
STEP 4: Clear the Data Path Resets and the Port Power-Down bit.
The default value of the Data Path Resets is one, which keeps the internal logic in the reset status. The user needs
to clear the following bits:
STEP 5: Configure the CLAD
STEP 6: Select the clock source for the transmitter.
STEP 7: Configure the Framing Mode and the Line Mode..
STEP 8: Disable Payload AIS (downstream AIS) and Line AIS
STEP 9: Enable each port (for non-LIU modes)
o
o
o
o
Framer: C-bit DS3
LIU: Disabled
GL.CR1.RSTDP = 0
PORT.CR1.RSTDP = 0
PORT.CR1.PD = 0
If using the LIU, configure the CLAD (which supplies the clock to the Receive LIU) via the CLAD bits in
the
Note: The user must supply a DS3, E3, or STS-1 clock to the CLKA pin.
Loop Time (use the receive clock): Set PORT.CR3.LOOPT = 1
CLAD Source: Set PORT.CR3.CLADC = 0
TCLKI Source: Set PORT.CR3.CLADC = 1
If using the CLAD, properly configure the CLAD by setting the CLAD bits in
PORT.CR2.LM[2:0] = 011 (LIU on, JA in Rx side) or another setting. See
PORT.CR2.FM[2:0] set to correct mode. See
PORT.CR1.PAIS[2:0] = 111
PORT.CR1.LAIS[1:0] = 11
PORT.CR2.TLEN = 1
GL.CR2
DS3171 rev 1.0:
DS3172 rev 1.0:
DS3173 rev 1.0:
DS3174 rev 1.0:
register.
0044h
0045h
0046h
0047h
Table 10-25.
48
Table 10-26
GL.CR2.