DS3171N+ Maxim Integrated Products, DS3171N+ Datasheet - Page 224

• Manufacturer Part Number: DS3171N+
• Description: TXRX SGL DS3/E3 400PBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3171N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 273mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: 90-31710+N00

18.1 Framer AC Characteristics
All AC timing characteristics are specified with a 25 pF capacitive load on all output pins, V
The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in
Figure
Table 18-1. Framer Port Timing
(V
Note 1: Any mode, 52MHz TCLKIn, RLCLKn input clocks.
Note 2: Any mode, TCLKIn, RLCLKn input clocks.
Note 3: TCLKIn, RLCLKn clock inputs to TOHMIn/TSOFIn, TFOHn/TSERn inputs.
Note 4: TCLKOn, RCLKOn clock outputs to TOHMIn/TSOFIn, TFOHn/TSERn inputs.
Note 5: TCLKIn, RLCLKn clock input to TSOFOn/TDENn, RSERn, RSOFOn/RDENn outputs.
Note 6: TCLKOn, RCLKOn clock output to TSOFOn/TDENn, RSERn, RSOFOn/RDENn outputs.
18.2 Line Interface AC Characteristics
All AC timing characteristics are specified with a 25 pF capacitive load on all output pins, V
The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in
Figure
Table 18-2. Line Interface Timing
(V
Note 1: Any mode, 52MHz TCLKIn, RLCLKn input clocks.
Note 2: Any mode, TCLKIn, RLCLKn input clocks.
Note 3: RLCLKn clock inputs to RPOSn/RDATn, RNEGn/RLCVn/ROHMIn inputs.
Note 4: TCLKIn, RLCLKn clock input to TPOSn/TDATn, TNEGn/TOHMOn outputs.
Note 5: TLCLKn, TCLKOn, RCLKOn clock output to TPOSn/TDATn, TNEGn/TOHMOn outputs.
CLK Period
CLK Clock Duty Cycle (t2/t1)
CLK Rise or Fall Times (20% to 80%)
DIN to CLK Setup Time
CLK to DIN Hold Time
CLK to DOUT Delay
CLK Period
CLK Clock Duty Cycle (t2/t1)
CLK Rise or Fall Times (20% to 80%)
DIN to CLK Setup Time
CLK to DIN Hold Time
CLK to DOUT Delay
DD
DD
= 3.3V ±5%, T
= 3.3V ±5%, T
18-2,
18-2,
Figure
Figure
PARAMETER
PARAMETER
j
j
18-3, and
18-3, and
= -40°C to +85°C.)
= -40°C to +85°C.)
Figure 18-6
Figure 18-6
apply to this
apply to this
SYMBOL
SYMBOL
t2/t1
t1
t3
t5
t6
t7
t2/t1
t1
t3
t5
t6
t7
interface.
interface.
224
Note 1
Note 2
Note 2
Note 3
Note 3
Note 4
Note 5
Note 1
Note 2
Note 3
Note 4
Note 3
Note 4
Note 5
Note 6
Note 2
CONDITIONS
CONDITIONS
19.23
19.23
MIN
MIN
40
40
3
7
1
1
2
2
4
0
2
2
TYP
TYP
IH
IH
50
50
= 2.4V and V
= 2.4V and V
MAX
MAX
60
11
60
10
4
9
4
8
Figure
Figure
IL
IL
UNITS
UNITS
= 0.8V.
= 0.8V.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
18-1,
18-1,