HBLXT9785EHC.B2 Intel, HBLXT9785EHC.B2 Datasheet - Page 115

• Manufacturer Part Number: HBLXT9785EHC.B2
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2

• Lead Free Status / Rohs Status: Not Compliant

4.0
4.1
4.1.1
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Note: Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E.
Functional Description
Introduction
The Intel
10 Mbps and 100 Mbps networks, complying with all applicable requirements of IEEE 802.3
standards. The device incorporates a Serial Media Independent Interface (SMII), Source
Synchronous-Serial Media Independent Interface (SS-SMII), and a Reduced Serial Independent
Interface (RMII) to enable each individual network port to interface with multiple 10/100 MACs.
Each port directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785/9785E
also supports 100BASE-FX operation via an LVPECL interface. The device has a 241-ball BGA, a
208-pin QFP, or a 196-ball BGA package.
The 196-ball BGA package (BGA15) is a reduced feature-set product designated as the
LXT9785MBC. The BGA15 package does not support the following features:
OSP™ Architecture
The Intel LXT9785/LXT9785E incorporates high-efficiency Optimal Signal Processing™ design
techniques, combining the best properties of digital and analog signal processing to produce a truly
optimal device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result
is improved receiver noise and cross-talk performance.
The OSP architecture also requires substantially less computational logic than traditional DSP-
based designs. The result is lower power consumption and reduced logic switching noise generated
by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable
source of EMI when generated from the device’s power supplies.
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RMII
Fiber
Sectionalization
Hardware control pins:
Extended temperature
— PAUSE
— MDIX
— MDDIS
— PWRDWN
— Lower three PHY address (out of five PHY address bits)
®
LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
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