HBLXT9785EHC.B2 Intel, HBLXT9785EHC.B2 Datasheet - Page 15

• Manufacturer Part Number: HBLXT9785EHC.B2
• Manufacturer: Intel

Specifications of HBLXT9785EHC.B2

• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Page
176
200
201
204
205
207
207
209
212
214
215
216
227
Page
211
109
129
131
133
110
111
112
112
114
49
70
1
Description
Modified Table 58 “Intel
Modified Table 83 “Control Register (Address 0)”.
Modified Table 84 “Status Register (Address 1)”.
Modified Table 87 “Auto-Negotiation Advertisement Register (Address 4)”.
Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 5)”.
Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address 8)”.
Modified Table 92 “Port Configuration Register (Address 16, Hex 10)”.
Modified Table 93 “Quick Status Register (Address 17, Hex 11)”.
Modified Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
Modified Table 95 “Interrupt Status Register (Address 19, Hex 13)”. Changed all references of RO/
SC to R/LH.
Modified Table 97 “Receive Error Count Register (Address 21, Hex 15)”.
Modified Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex 19)”. Added note to
Register bit 25.0.
Modified Table 99 “Trim Enable Register (Address 27, Hex 1B)”.
Modified Table 103 “Product Information”.
Description
Added bullet to Product Features
Modified Table 12 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added
FIFOSEL1 and FIFOSEL0)
Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode”
Modified Figure 38 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver
Interface Circuitry”
Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Circuitry”
Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”
Modified Table 28 “Absolute Maximum Ratings”
Modified Table 29 “Operating Conditions”
Modified Table 31 “Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)”(Output low
voltage SD pins - Max)
Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX
Receive Timing Parameters”
Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX
Receive Timing Parameters”
Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive
Timing Parameters”
Revision Number: 006 (INTERNAL RELEASE)
®
LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.
Revision Date: June 10, 2003
Revision Date: January 2002
Revision Number: 005
(Sheet 2 of 2)
(Sheet 1 of 2)
Contents
15