AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 34

• Manufacturer Part Number: AT89LP4052
• Manufacturer: Atmel Corporation

Specifications of AT89LP4052

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 15
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI
• Watchdog: Yes

18.3
34
More About Mode 0
AT89LP2052/LP4052
Table 18-2
Table 18-2.
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are trans-
mitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency.
18-1
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads a “1” into the ninth position of the transmit shift register and tells the
TX Control block to begin a transmission. The internal timing is such that one full machine cycle
will elapse between “write to SBUF” and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and
also transfers Shift Clock to the alternate output function line of P3.1. At the falling edge of Shift
Clock the contents of the transmit shift register are shifted one position to the right.
As data bits shift out to the right, “0”s come in from the left. When the MSB of the data byte is at
the output position of the shift register, the “1” that was initially loaded into the ninth position is
just to the left of the MSB, and all positions to the left of that contain “0”s. This condition flags the
TX Control block to do one last shift, then deactivate SEND and set TI.
Reception is initiated by the condition REN = 1 and R1 = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next
clock phase.
RECEIVE enables Shift Clock to the alternate output function line of P3.1. At the falling edge of
Shift Clock the contents of the receive shift register are shifted one position to the left. The value
that comes in from the right is the value that was sampled at the P3.0 pin at rising edge of Shift
Clock.
As data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded
into the right-most position arrives at the left-most position in the shift register, it flags the RX
Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
Mode 0: 1 MHz
Mode 2: 375K
Baud Rate
shows a simplified functional diagram of the serial port in Mode 0 and associated timing.
62.5K
19.2K
137.5
9.6K
4.8K
2.4K
1.2K
110
110
lists commonly used baud rates and how they can be obtained from Timer 1.
Commonly Used Baud Rates Generated by Timer 1
f
OSC
11.059
11.059
11.059
11.059
11.059
11.986
12
12
12
(MHz)
2
6
SMOD1
X
0
1
1
0
0
0
0
0
0
0
C/T
X
X
0
0
0
0
0
0
0
0
0
Mode
Timer 1
X
X
2
2
2
2
2
1
1
1
1
3547J–MICRO–10/09
Reload Value
FEE0H
F55CH
F958H
F304H
DCH
DCH
F4H
B8H
70H
X
X
Figure