AT89LP4052 Atmel Corporation, AT89LP4052 Datasheet - Page 59

• Manufacturer Part Number: AT89LP4052
• Manufacturer: Atmel Corporation

Specifications of AT89LP4052

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 15
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI
• Watchdog: Yes

23.2
Table 23-2.
23.3
23.4
3547J–MICRO–10/09
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Bit
Status Register
DATA Polling
Parallel Programming
Function
Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that
the page buffer was previously loaded with data by the load page buffer command.
Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle
completes without interruption from the brownout detector.
Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V
below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag
will remain low after the cycle is complete. WRTINH low also forces BUSY low.
Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.
Status
–
7
Register
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
The AT89LP2052/LP4052 implements DATA polling to indicate the end of a programming cycle.
While the device is busy, any attempted read of the last byte written will return the data byte with
the MSB complemented. Once the programming cycle has completed, the true value will be
accessible. During Erase the data is assumed to be FFH and DATA polling will return 7FH.
When writing multiple bytes in a page, the DATA value will be the last data byte loaded before
programming begins, not the written byte with the highest physical address within the page.
Parallel Programming Mode is enabled by applying V
required during parallel mode are shown in
configured as an 8-bit wide bidirectional command bus. Data on P1 is strobed by a positive
pulse on the XTAL1 pin. No other clock is required. The interface is enabled by pulling CS (P3.2)
low. P3.1 acts as RDY/BSY, and will be pulled low to indicate that the device is busy regardless
of the state of CS.
–
6
Table
–
5
23-2.
–
4
LOAD
Figure
3
23-2. During parallel programming, Port 1 is
SUCCESS
AT89LP2052/LP4052
2
PP
to the RST pin. The connections
WRTINH
1
BUSY
0
CC
falling
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