ATmega3250A Atmel Corporation, ATmega3250A Datasheet - Page 109

• Manufacturer Part Number: ATmega3250A
• Manufacturer: Atmel Corporation

Specifications of ATmega3250A

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16. 16-bit Timer/Counter1
16.1
16.2
8285D–AVR–06/11
Features
Overview
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the Timer/Counter number, and a
lower case “x” replaces the Output Compare unit number. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing
Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
p l a c e m e n t o f I / O p i n s , r e f e r t o
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P” on
page
device-specific I/O Register and bit locations are listed in the
130.
The PRTIM1 bit in
enable Timer/Counter1 module
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
”PRR – Power Reduction Register” on page 45
” 6 4 A ( T Q F P ) a n d 6 4 M 1 ( Q F N / M L F ) P i n o u t
”Register Description” on page
Figure
must be written to zero to
16-1. For the actual
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