ATmega3250A Atmel Corporation, ATmega3250A Datasheet - Page 246

• Manufacturer Part Number: ATmega3250A
• Manufacturer: Atmel Corporation

Specifications of ATmega3250A

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.5.4
8285D–AVR–06/11
Scanning the Analog Comparator
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Table 25-1 on page 246
tors with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 25-1.
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
246. The Boundary-scan cell from
The signals are described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Figure 25-7. Analog Comparator
Enable Signal
EXTCLKEN
OSCON
OSC32EN
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided.
Scan Signals for the Oscillator
ADCEN
ACME
Scanned
Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
ADC MULTIPLEXER
summaries the scan registers for the external clock pin XTAL1, oscilla-
REFERENCE
BANDGAP
OUTPUT
Table 25-2 on page
Figure 25-8 on page 247
ACBG
Clock Option
External Clock
External Crystal
External Ceramic Resonator
Low Freq. External Crystal
(1)(2)(3)
247.
ACD
AC_IDLE
is attached to each of these signals.
Scanned Clock Line
Figure 25-7 on page
ACO
when not Used
1
0
1
246