ATtiny24A Atmel Corporation, ATtiny24A Datasheet - Page 123

• Manufacturer Part Number: ATtiny24A
• Manufacturer: Atmel Corporation

Specifications of ATtiny24A

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.5
14.5.1
8183D–AVR–04/11
Alternative USI Usage
Register Descriptions
Half-Duplex Asynchronous Data Transfer
4-Bit Counter
12-Bit Timer/Counter
Edge Triggered External Interrupt
Software Interrupt
USICR – USI Control Register
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the
clock and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt
and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed
immediately. Refer to the USISIF bit description on
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and
USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-
diately. Refer to the USIOIF bit description on
• Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used, as shown in
Basically, only the function of the outputs are affected by these bits. Data and clock inputs are
not affected by the mode selected and will always have the same function. The counter and USI
Bit
0x0D (0x2D)
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
6
0
USIWM1
R/W
5
0
USIWM0
R/W
4
0
page 126
page 125
USICS1
R/W
3
0
for further details.
ATtiny24A/44A/84A
Table 14-1 on page
for further details.
USICS0
R/W
2
0
USICLK
W
1
0
USITC
124.
W
0
0
USICR
123