ATtiny24A Atmel Corporation, ATtiny24A Datasheet - Page 279

• Manufacturer Part Number: ATtiny24A
• Manufacturer: Atmel Corporation

Specifications of ATtiny24A

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

27. Datasheet Revision History
27.1
27.2
27.3
8183D–AVR–04/11
Rev. 8183D – 04/11
Rev. 8183C – 03/11
Rev. 8183B – 03/10
1. Added errata for ATtiny44A rev. G in
1. Added:
2. Updated:
1. Updated template.
2. Added UFBGA package (15CC1) in:
3. Separated typical characteristic plots, added
4. Updated sections:
5. Updated Figures:
6. Updated Tables:
– ATtiny84A, including typical characteristics plots
–
–
– Analog Comparator Offset plots for ATtiny24A
– Extended temperature part numbers in
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]
–
–
–
–
page
page
–
–
–
–
–
–
–
Section 3.3 “Capacitive Touch Sensing” on page 6
Table 6-8, “Capacitance of Low-Frequency Crystal Oscillator,” on page 28
ATtiny44A
270
Section 6.4 “Clock Output Buffer” on page
Table 16-4, “Single-Ended Input channel Selections,” on page
Internal 1.1V Reference
Table 19-16, “High-voltage Serial Programming Instruction Set for
ATtiny24A/44A/84A,” on page
Table 20-1, “DC Characteristics. TA = -40°C to +85°C,” on page
Section 14.5.4 “USIBR – USI Buffer Register” on page
Section 24. “Ordering Information” on page
marking, updated notes
Figure 4-1 “Block Diagram of the AVR Architecture” on page 7
Figure 8-1 “Reset Logic” on page 38
Figure 14-1 “Universal Serial Interface, Block Diagram” on page
USIBR
Figure 19-5 “High-voltage Serial Programming Waveforms” on page 169
Table 19-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM
Location,” on page
2,
275.
Section 24. “Ordering Information” on page
(Figure 21.3.11 on page
164, updated value for t
170, adjusted notes
Section 26. “Errata” on page 278
“Features” on page
236)
Section 24. “Ordering Information” on page
30, changed CLKO to CKOUT
Section 21.2 “ATtiny24A” on page
WD_ERASE
270, added tape & reel and topside
(Figure 21.2.10 on page
270, and
ATtiny24A/44A/84A
1,
127, header updated
“Pin Configurations” on
Section 25.3 “15CC1” on
145, added note for
173, adjusted notes
116, USIDB ->
208) and
183.
279