ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 360

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.7
28.8
28.9
8331A–AVR–07/11
Compare function
Starting a conversion
ADC Clock and Conversion Timing
The ADC has a built in 12-bit compare function. The ADC compare register can hold a 12-bit
value that represents a threshold voltage. Each ADC Channel can be configured to automati-
cally compare its result with this compare value to give an interrupt or event only when the result
is above or below the threshold.
All four ADC Channels share the same compare register.
Before a conversion is started, the input source must be selected for one or more ADC channel.
An ADC conversion for a Channel can either be started by the application software writing to the
start conversion bit for the Channel, or from any events in the Event System. It is possible to
write the start conversion bit for several Channels at the same time, or to use one event to trig-
ger conversions on several Channels at the same time. This makes it possible to scan several or
all Cchannels from one event.
The ADC is clocked from the Peripheral Clock. The ADC can prescale the Peripheral Clock to
provide an ADC Clock (Clk
operating range of the ADC.
Figure 28-12. ADC Prescaler
The maximum ADC sample rate is given by the he ADC clock frequency (f
sample a new measurement on every ADC clock cycle.
The propagation delay of an ADC measurement is given by:
RES is the resolution, 8- or 12-bit. The propagation delay will increase by one extra ADC clock
cycle if the Gain Stage (GAIN) is used.
The propagation delay is longer than one ADC clock cycle, but the pipelined design means that
the sample rate is not limited by the propagation delay, but by the ADC clock rate.
Sample Rate
Propagation Delay =
=
f
ADC
1
----------------------------------------- -
+
RES
---------- -
2
f
ADC
+
ADC
PRESCALER[2:0]
GAIN
) that matches the application requirements, and is within the
Clk
PER
9-bit ADC Prescaler
Atmel AVR XMEGA AU
Clk
ADC
ADC
). The ADC can
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