ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 378

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.17.5.1
28.17.5.2
28.17.5.3
28.17.6
28.17.6.1
28.17.6.2
28.17.7
8331A–AVR–07/11
RESL – Channel n Result register Low
SCAN – Channel Scan Register
12-bit mode, left adjusted
12-bit mode, right adjusted
8-bit mode
12-/8-bit mode
12-bit mode, left adjusted
• Bit 7:0 – RES[11:4]: ADC Channel Result, high byte
These are the 8 MSB of the 12-bit ADC result.
• Bit 7:4 – Reserved
These bits will in practice be the extension of the sign bit CHRES11 when ADC works in differen-
tial mode and set to zero when ADC works in signed mode.
• Bits 3:0 – RES[11:8]: ADC Channel Result, high byte
These are the 4 MSB of the 12-bit ADC result.
• Bit 7:0 – Reserved
These bits will in practice be the extension of the sign bit CHRES7 when ADC works in signed
mode and set to zero when ADC works in single-ended mode.
• Bit 7:0 – RES[7:0]: ADC Channel Result, low byte
These are the 8 LSB of the ADC result.
• Bit 7:4 – RES[3:0]: ADC Channel Result, low byte
These are the 4 LSB of the 12 bit ADC result.
• Bit 3:0 – Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Scan is enabled when COUNT is set different than 0. This register is only available for ADC
Channel 0.
12-/8-bit, right
12-bit, left.
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
R/W
7
0
R/W
6
0
R
7
0
OFFSET[3:0]
R/W
5
0
R
6
0
RES[3:0]
R/W
4
0
R
5
0
Atmel AVR XMEGA AU
R/W
3
0
R
4
0
RES[7:0]
R/W
2
0
R
3
–
0
COUNT[3:0]
R/W
R
1
0
2
–
0
R/W
R
0
0
1
–
0
SCAN
R
0
–
0
378