ATxmega256A3U Atmel Corporation, ATxmega256A3U Datasheet - Page 86

• Manufacturer Part Number: ATxmega256A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3U

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 7-5.
7.6
8331A–AVR–07/11
External Oscillator or Clock.
Internal 32.768kHz Osc.
Internal 32MHz Osc.
Internal 2MHz Osc.
PLL with 1x-31x Multiplication Factor
Internal PLL.
System clock selection and prescalers.
Clock Selection
Prescaler A divides the system clock, and the resulting clock is clk
be enabled to divide the clock speed further to enable peripheral modules to run at twice or four
times the CPU clock frequency. If Prescalers B and C are not used, all the clocks will run at the
same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change
protection mechanism, employing a timed write procedure for changing the system clock and
prescaler settings. For details, refer to
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock.
The PLL has a user-selectable multiplication factor of from 1 to 31. The output frequency, f
given by the input frequency, f
Four different clock sources can be chosen as input to the PLL:
To enable the PLL, the following procedure must be followed:
1. Enable reference clock source.
2. Set the multiplication factor and select the clock reference for the PLL.
3. Wait until the clock reference source is stable.
4. Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The
PLL must be disabled before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stable and the PLL has
locked.
The reference clock source cannot be disabled while the PLL is running.
Clk
• 2MHz internal oscillator
• 32MHz internal oscillator divided by 4
• 0.4MHz - 16MHz crystal oscillator
• External clock
SYS
1, 2, 4, ... , 512
Prescaler A
Clk
Prescaler B
IN
PER4
, multiplied by the multiplication factor, PLL_FAC.
1, 2, 4
f
”Configuration Change Protection” on page
OUT
=
f
IN
⋅
PLL_FAC
Clk
Prescaler C
Atmel AVR XMEGA AU
PER2
1, 2
PER4
Clk
Clk
CPU
PER
. Prescalers B and C can
12.
OUT
, is
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