SAM9261 Atmel Corporation, SAM9261 Datasheet
SAM9261
Specifications of SAM9261
Related parts for SAM9261
SAM9261 Summary of contents
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... Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals ® ® Thumb Processor ® Acceleration ™ ® AT91 ARM Thumb-based Microcontrollers AT91SAM9261 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6062LS–ATARM–23-Mar-09 ...
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... Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 217-ball LFBGA RoHS-compliant Package AT91SAM9261 2 Compliant ® Infrared Modulation/Demodulation 6062LS–ATARM–23-Mar-09 ...
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... DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz. The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its inte- grated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance ...
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... Block Diagram Figure 2-1. AT91SAM9261 Block Diagram JTAGSEL TDI JTAG TDO TMS Boundary Scan TCK NTRST RTCK System Controller TST AIC FIQ IRQ0-IRQ2 DRXD DBGU DTXD PDC PCK0-PCK3 PLLRCA PLLA PLLRCB PMC PLLB XIN OSC XOUT WDT PIT GPBREG XIN32 OSC RTT ...
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... Input Output Input Output Input Input Low Input ™ ETM Output Output Output Output AT91SAM9261 Comments 1. 1.95V and 3.0V to 3.6V 2.7V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Do not tie over VDDBU. Accepts between 0V and VDDBU. No pull-up resistor. No pull-up resistor. No pull-up resistor. No pull-up resistor. ...
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... CFIOW CompactFlash IO Write CFRNW CompactFlash Read Not Write CFCS0 - CFCS1 CompactFlash Chip Select Lines NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDCS NAND Flash Chip Select AT91SAM9261 6 Type Active Level Reset/Test I/O Low Input Input Debug Unit Input Output ...
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... Type Active Level SDRAM Controller Output Output High Output Low Output Output Low Output Low Output Multimedia Card Interface Output I/O I/O USART I/O Output Input Output Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O SPI I/O I/O I/O I/O Low Output Low AT91SAM9261 Comments 7 ...
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... USB Device Port Data - DDP USB Device Port Data + HDMA USB Host Port A Data - HDPA USB Host Port A Data + HDMB USB Host Port B Data - HDPB USB Host Port B Data + AT91SAM9261 8 Type Active Level Two-Wire Interface I/O I/O LCD Controller Output Output Output Output ...
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... Package and Pinout The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9261 Mechanical Character- istics” of the product datasheet. Figure 4-1. 6062LS–ATARM–23-Mar-09 shows the orientation of the 217-ball LFBGA Package. ...
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... Pinout Table 4-1. AT91SAM9261 Pinout for 217-ball LFBGA Package Pin Signal Name Pin A1 A19 D5 A2 A16/BA0 D6 A3 A14 D7 A4 A12 D10 A7 A3 D11 A8 A2 D12 A9 NC D13 A10 XOUT32 D14 A11 XIN32 D15 A12 DDP D16 A13 HDPB D17 ...
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... GNDBU, GNDOSC and GNDPLL, respectively. 5.2 Power Consumption The AT91SAM9261 consumes about 550 µA of static current on VDDCORE at 25°C. This static current rises 5 the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise µA @85°C. ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU. AT91SAM9261 12 6062LS–ATARM–23-Mar-09 ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6062LS–ATARM–23-Mar-09 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9261 13 ...
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... Selection is made by BMS pin sampled at reset. • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors AT91SAM9261 14 ™ Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. ...
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... Next Pointer Support, forbids strong real-time constraints on buffer management. • Nineteen channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface 6062LS–ATARM–23-Mar-09 AT91SAM9261 15 ...
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... Memories Figure 8-1. AT91SAM9261 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Supports ARM926EJ-S TCM interface at full processor speed 6062LS–ATARM–23-Mar-09 ™ Instruction and Data), three different Slaves are Table 8-3 for details. List of Bus Matrix Masters List of Bus Matrix Slaves AT91SAM9261 ARM926 Instruction ARM926 Data PDC LCD Controller USB Host Internal SRAM Internal ROM ...
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... Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 8.1.1.1 Internal SRAM The AT91SAM9261 embeds a high-speed 160 Kbyte SRAM. This Internal SRAM is split into three areas. Its Memory Mapping is detailed in • Internal SRAM A is the ARM926EJ-S Instruction TCM and the user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions ...
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... Note: 1. Configuration after reset. 8.1.1.2 Internal ROM The AT91SAM9261 integrates a 32 Kbyte Internal ROM mapped at address 0x0040 0000 also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset. 8.1.1.3 USB Host Port The AT91SAM9261 integrates a USB Host Port Open Host Controller Interface (OHCI). The reg- isters of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000 ...
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... When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. ...
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... Fetch Internal Data Internal Fetch External Data External Fetch Internal Data Internal Data Figure 8-1 on page AT91SAM9261 Table 8-6. Start Address End Address 0x0000 0000 0x002F FFFF 0x0000 0000 0x002F FFFF 0x0040 0000 0x004F FFFF 0x0040 0000 0x004F FFFF 0x1000 0000 0x8FFF FFFF ...
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... EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 23 Figure 8-1 on page 16 peripherals. AT91SAM9261 22 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6062LS–ATARM–23-Mar-09 ...
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... Power Management UHPCK PLLACK Controller LCDCK MCK PLLBCK pmc_irq int idle periph_irq{2..4] irq0-irq2 dbgu_rxd PIO fiq Controllers dbgu_txd AT91SAM9261 nirq nfiq ice_nreset ntrst ARM926EJ-S force_ntrst proc_nreset PCK debug jtag_nreset Boundary Scan TAP Controller MCK Bus Matrix periph_nreset UDPCK periph_clk[10] USB Device ...
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... Embeds Two PLLs – Outputs 80 to 240 MHz clocks – Integrates an input divider to increase output accuracy – 1 MHz minimum input frequency • Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. AT91SAM9261 24 Clock Generator Block Diagram Clock Generator XIN32 Slow Clock Oscillator ...
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... Divider Prescaler MAINCK /1,/2,/4 PLLACK /1,/2,/4,...,/64 PLLBCK Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK PLLBCK ® ® /WindowsCE compliant tick generator AT91SAM9261 Processor Clock PCK Controller int Idle Mode MCK APB Peripherals Clock Controller periph_clk[2..21] ON/OFF AHB Peripherals Clock Controller HCKx ON/OFF Prescaler pck[0 ...
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... Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support AT91SAM9261 26 interrupts processor Generator ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 6062LS–ATARM–23-Mar-09 peripherals AT91SAM9261 27 ...
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... Note: AT91SAM9261 28 Figure 8-1 on page defines the Peripheral Identifiers of the AT91SAM9261. A peripheral identifier is Peripheral Identifiers Peripheral Mnemonic Peripheral Name AIC Advanced Interrupt Controller SYSIRQ System Interrupt PIOA Parallel I/O Controller A PIOB Parallel I/O Controller B PIOC Parallel I/O Controller C - Reserved ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions page 33 lers. The two columns “Function” and “Comments” have been inserted for the user’s own comments ...
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... Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.10 Interrupt Lines • Using FIQ prevents using the USART0 control signals. • Using IRQ0 prevents using the NWAIT EBI signal. • Using the IRQ1 and/or IRQ2 prevents using the SPI1. AT91SAM9261 30 6062LS–ATARM–23-Mar-09 ...
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... Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP A23 VDDIOP A24 VDDIOP AT91SAM9261 Function Comments 31 ...
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... PB27 SPI1_NPCS1 LCDD22 PB28 SPI1_NPCS0 LCDD23 PB29 SPI1_SPCK IRQ2 PB30 SPI1_MISO IRQ1 PB31 SPI1_MOSI PCK2 Note: 1. PB3 is multiplexed with BMS signal. Care should be taken during reset time. AT91SAM9261 32 Application Usage Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP (1) See footnote I/O VDDIOP ...
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... Reset Comments State Power Supply I/O VDDIOP I/O VDDIOP I/O VDDIOP A25 VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOP I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM I/O VDDIOM AT91SAM9261 Function Comments 33 ...
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... Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7 AT91SAM9261 34 IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. ...
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... Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency and 3 supported • Auto Precharge Command not used 6062LS–ATARM–23-Mar-09 AT91SAM9261 35 ...
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... RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps AT91SAM9261 36 fifteen peripherals Sensors and data per chip select ...
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... Each MCI has two slots, each supporting – One slot for one MultiMedia Card bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 6062LS–ATARM–23-Mar-09 AT91SAM9261 2 S, TDM Buses, Magnetic Card Reader and 37 ...
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... STN • bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048 x 2048 AT91SAM9261 38 Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode ...
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... Package Drawing Figure 11-1. 217-ball LFBGA Package Drawing 6062LS–ATARM–23-Mar-09 AT91SAM9261 39 ...
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... Ordering Information Table 12-1. AT91SAM9261 Ordering Information Ordering Code MRL AT91SAM9261-CJ AT91SAM9261B-CU AT91SAM9261 40 Package Package Type A BGA217 RoHS-compliant B BGA217 Temperature Operating Range Industrial -40°C to 85°C Industrial Green -40°C to 85°C 6062LS–ATARM–23-Mar-09 ...
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... Section 6.4 “PIO Controller A, B and C Lines” on page Table 8-3, “Internal Memory Mapping,” on page Figure 2-1, “AT91SAM9261 Block Diagram,” on page 5, Table 10-2, “Multiplexing on PIO Controller A,” on page 33. Figure 2-1, “AT91SAM9261 Block Diagram,” on page Table 12-1, “AT91SAM9261 Ordering Information,” on page AT91SAM9261 “Features” on page 1. Change to Section 5.2 “Power 18. Table 3-1, “Signal Description by 4 ...
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... Figure 8-1, “AT91SAM9261 Memory Mapping,” on page Table 10-1, “Peripheral Identifiers,” on page and Section 5.2 “Power Consumption” on page Figure 8-1, “AT91SAM9261 Memory Mapping,” on page Section 9.6 “Power Management Controller” on page 25 25. Section 11. “Package Drawing” on page Strategies”, removed sentence pertaining to “remap” ...
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... In Features, on page 2 6062KS Debug Unit (DBGU) updated 5932 Section 10.9 5424/rfo Section 8.1.2.1 “BMS = 1, Boot on Embedded 6062LS Section 12. “Ordering updated with ordering information for chip revision B. 6062LS–ATARM–23-Mar-09 “USART”, manchester encoding option is not avaiilable. ROM”, updated. Information”, AT91SAM9261 43 ...
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