SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 171

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.6
ARM DDI 0165B
Thumb Branch, Link, and Exchange <immediate>
A Thumb Branch, Link, and Exchange immediate (
similar to a Thumb
takes four cycles:
1.
2.
Table 8-7 shows the cycle timings of the complete operation.
Cycle
1
2
3
4
The first instruction acts as a simple data operation. It takes a single cycle to add
The second instruction acts similarly to the ARM
the PC to the upper part of the offset, and stores the result in r14. If the previous
instruction requested a data memory access, the data is transferred in this cycle.
a.
b.
c.
Copyright © 2000 ARM Limited. All rights reserved.
IA
pc+3i
pc’
pc’+i
pc’+2i
During the first cycle, the ARM9E-S calculates the final branch target
address while performing a prefetch from the current PC.
During the second cycle, the ARM9E-S performs a fetch from the branch
destination, using the new instruction width, dependent on the state that has
been selected. The return address to be stored in r14 is calculated.
During the third cycle, the ARM9E-S performs a fetch from the destination
+ 4, refilling the instruction pipeline.
BL
InMREQ,
ISEQ
S cycle
N cycle
S cycle
S cycle
operation. It comprises two consecutive Thumb instructions, and
Table 8-7 Thumb branch, link and exchange cycle timing
INSTR
(pc+2i)
(pc+3i)
(pc’)
(pc’+i)
(pc’+2i)
ITBIT
t
t’
t’
t’
BLX <immediate>
DA
-
-
-
-
BLX
instruction:
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
I cycle
Instruction Cycle Times
) operation is
RDATA/
WDATA
-
-
-
-
8-11