AD7851 Analog Devices, AD7851 Datasheet - Page 12

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AD7851

Manufacturer Part Number
AD7851
Description
14-Bit, 333 kSPS, Serial Sampling A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD7851

Resolution (bits)
14bit
# Chan
1
Sample Rate
333kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(Vref) p-p,Uni (Vref)
Adc Architecture
SAR
Pkg Type
DIP,SOIC,SOP

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AD7851
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register is described below. The power-up status of all bits is 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit No. Mnemonic
ZERO
BUSY
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
2/3 MODE
X
CALMD
CALSLT1
CALSLT0
STCAL
RDSLT1
ZERO
MSB
Comment
This bit is always 0.
Conversion/Calibration Busy Bit. When this bit is 1, this indicates that there is a conversion or calibration
in progress. When this bit is 0, there is no conversion or calibration in progress.
These four bits are always 0.
Power Management Bits. These bits along with the SLEEP pin will indicate whether the part is in a power-
down mode. (See Table VI in the Power-Down Options section for description.)
Both these bits are always 1 indicating it is the status register that is being read. (See Table II.)
Interface Mode Select Bit. With this bit 0, the device is in Interface Mode 2. With this bit 1, the device is in
Interface Mode 1. This bit is reset to 0 after every read cycle.
Don’t care bit.
Calibration Mode Bit. A 0 in this bit indicates self-calibration is selected, and 1 in this bit indicates a system
calibration is selected (see Table III).
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in
progress and as a 0 if there is no calibration in progress. The CALSLT1 and CALSLT0 bits indicate which
of the calibration registers are addressed for reading and writing (see the Calibration Registers section for
more details)
RDSLT0
BUSY
Figure 6. Flowchart for Reading the Status Register
2/3 MODE
ZERO
Status Register Bit Function Descriptions
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
ZERO
X
START
–12–
CALMD
ZERO
CALSLT1
ZERO
CALSLT0
PMGT1
PMGT0
STCAL
LSB
REV. B

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