AD7851 Analog Devices, AD7851 Datasheet - Page 27

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

MODE 4 and 5 (Self-Clocking Modes)
The timing diagrams in Figure 38 and Figure 39 are for Inter-
face Modes 4 and 5. Interface Mode 4 has a noncontinuous
SCLK output and Interface Mode 5 has a continuous SCLK
output (SCLK is switched off internally during calibration for
both Modes 4 and 5). These modes of operation are especially
different from all the other modes because the SCLK and
SYNC are outputs. The SYNC is generated by the part as is the
SCLK. The master clock at the CLKIN pin is routed directly to
the SCLK pin for Interface Mode 5 (continuous SCLK) and the
CLKIN signal is gated with the SYNC to give the SCLK (non-
continuous) for Interface Mode 4.
The most important point about these two modes of operation
is that the result of the current conversion is clocked out during
the same conversion and a write to the part during this conver-
sion is for the next conversion. The arrangement is shown in
Figure 37. Figure 38 and Figure 39 show more detailed timing
for the arrangement of Figure 37.
In Figure 38 the first point to note is that the BUSY, SYNC,
and SCLK are all outputs from the AD7851 with the CONVST
being the only input signal. Conversion is initiated with the
CONVST signal going low. This CONVST falling edge also
triggers the BUSY to go high. The CONVST signal rising edge
triggers the SYNC to go low after a short delay (2.5 t
3.5 t
data on the DOUT pin during conversion. The data on the DIN
pin is also clocked in to the AD7851 by the same SCLK for the
next conversion. The read/write operations must be complete
after 16 clock cycles (which takes 3.25 µs approximately from
the rising edge of CONVST assuming a 6 MHz CLKIN). At
REV. B
Figure 39. Mode 4 and 5 Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and
Noncontinuous, SM1 = 1, SM2 = 1 and 0)
CLKIN
CONVERSION N
typically) after which the SCLK will clock out the
3.25 s
DOUT (O/P)
WRITE N+1
SYNC (O/P)
SCLK (O/P)
THE CONVERSION RESULT DUE TO
READ N
DIN (I/P)
WRITE N+1 IS READ HERE
POLARITY PIN
LOGIC HIGH
THREE-STATE
CONVERSION N+1
Figure 37.
C
3.25 s
t
5
WRITE N+2
READ N+1
DB15
t
7
t
4
t
t
4
7
DB15
= 0.6 t
= 30ns MIN, t
1
t
DB14
8
SCLK
CONVERSION N+2
DB14
(NONCONTINUOUS SCLK), t
2
8
3.25 s
WRITE N+3
= 20ns MIN , t
READ N+2
CLKIN
DB13
t
9
DB13
t
to
3
10
DB12
11A
–27–
= 50ns MAX
DB12
4
this time, the conversion will be complete, the SYNC will go
high, and the BUSY will go low. The next falling edge of the
CONVST must occur at least 330 ns after the falling edge of
BUSY to allow the track-and-hold amplifier adequate acquisi-
tion time as shown in Figure 38. This gives a throughput time of
3.68 µs. The maximum throughput rate in this case is 272 kHz.
In these interface modes, the part is now the master and the
DSP is the slave. Figure 39 is an expansion of Figure 38. The
AD7851 will ensure SYNC goes low after the rising edge C of
the continuous SCLK (Interface Mode 5) in Figure 39. Only in
the case of a noncontinuous SCLK (Interface Mode 4) will the
time t
edge of SYNC. The SCLK rising edge clocks out all subsequent
bits on the DOUT pin. The input data present on the DIN pin
is clocked in on the rising edge of the SCLK. The POLARITY
pin may be used to change the SCLK edge which the data is
sampled on and clocked out on. The SYNC will go high after
the 16th SCLK rising edge and before the falling edge D of the
continuous SCLK in Figure 39. This ensures the part will not
clock in an extra bit from the DIN pin or clock out an extra bit
on the DOUT pin.
CONVST
DB11
SCLK
CONVERSION IS INITIATED
Figure 38. Mode 4 and 5 Timing Diagram (SM1 = 1,
SM2 = 1 and 0)
SYNC
BUSY
(O/P)
6
(O/P)
(O/P)
AND TRACK-AND-HOLD
(I/P)
= 45ns MAX,
4
GOES INTO HOLD
t
DB11
t
6
apply. The first data bit is clocked out from the falling
1
5
= 100ns MIN
DB10
t
1
DB10
t
8
6
t
CONVERT
= 3.25 s
SERIAL READ
OPERATIONS
AND WRITE
DB0
16
CONVERSION ENDS
DB0
OUTPUT SERIAL SHIFT
t
3.25 s LATER
12
REGISTER IS RESET
t
11A
400ns MIN
PRIOR TO NEXT RISING
THREE-STATE
SHOULD END 500ns
READ OPERATION
EDGE OF CONVST
D
AD7851