AD7851 Analog Devices, AD7851 Datasheet - Page 24

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7851
SERIAL INTERFACE SUMMARY
Table IX details the five interface modes and the serial clock
edges from which the data is clocked out by the AD7851
(DOUT edge) and that the data is latched in on (DIN edge).
The logic level of the POLARITY pin is shown and it is clear
that this reverses the edges.
In Interface Modes 4 and 5 the SYNC always clocks out the
first data bit and SCLK will clock out the subsequent bits.
In Interface Modes 1, 2, and 3 the SYNC is gated with the SCLK
and the POLARITY pin. Thus, the SYNC may clock out the
MSB of data. Subsequent bits will be clocked out by the serial
clock, SCLK. The conditions for the SYNC clocking out the
MSB of data is as follows.
With the POLARITY pin high, the falling edge of SYNC will
clock out the MSB if the serial clock is low when the SYNC
goes low.
With the POLARITY pin low, the falling edge of SYNC will
clock out the MSB if the serial clock is high when the SYNC
goes low.
Interface
Mode
1, 2, 3
4, 5
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The SYNC pin acts as a reset. Bringing the
SYNC pin high resets the internal shift register. The first data
bit after the next SYNC falling edge will now be the first bit of
a new 16-bit transfer. It is also possible that the test register
contents were altered when the interface was lost. Therefore,
once the serial interface is reset, it may be necessary to write
the 16-bit word 0100 0000 0000 0010 to restore the test regis-
ter to its default value. Now the part and serial interface are
completely reset. It is always useful to retain the ability to pro-
gram the SYNC line from a port of the µController/DSP to have
the ability to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7851. It also outlines the various µP/µC to which the par-
ticular interface is suited.
The interface mode is determined by the serial mode selection
Pins SM1 and SM2. Interface Mode 2 is the default mode.
Note that Interface Mode 1 and 2 have the same combination of
Table IX. SCLK Active Edge for Different Interface Modes
POLARITY
Pin
0
1
0
1
DOUT
Edge
SCLK ↑
SCLK ↓
SCLK ↓
SCLK ↑
DIN
Edge
SCLK ↓
SCLK ↑
SCLK ↑
SCLK ↓
–24–
SM1 and SM2. Interface Mode 1 may only be set by program-
ming the control register (see the Control Register section).
External SCLK and SYNC signals (SYNC may be hardwired
low) are required for Interfaces Modes 1, 2, and 3. In Interface
Modes 4 and 5, the AD7851 generates the SCLK and SYNC.
Some of the more popular µProcessors, µControllers, and the
DSP machines that the AD7851 will interface to directly are
mentioned here. This does not cover all µCs, µPs, and DSPs. The
interface mode of the AD7851 that is mentioned here for a
specific µC, µP, or DSP is only a guide and in most cases another
interface mode may work just as well.
A more detailed timing description on each of the interface
modes follows.
SM1
Pin
0
0
0
1
1
SM2
Pin
0
0
1
0
1
Table X. Interface Mode Description
8XC51
8XL51
PIC17C42
68HC11
68L11
68HC16
PIC16C64
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
TMS320C30
68HC16
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
TMS320C20
TMS320C25
TMS320C30
TMS320C5X
TMS320LC5X
Processor
Controller
Interface
Mode
1 (2-Wire)
DIN Is an Input/
Output Pin
2 (3-Wire, SPI/QSPI)
Default Mode
3 (QSPI)
External Serial
Clock, SCLK, and
External Frame Sync,
SYNC Are Required
4 (DSP Is Slave)
AD7851 Generates a
Noncontinuous
(16 Clocks) Serial
Clock, SCLK, and the
Frame Sync, SYNC
5 (DSP Is Slave)
AD7851 Generates a
Continuous Serial
Clock, SCLK, and the
Frame Sync, SYNC
REV. B