CS8406-DZZ Cirrus Logic Inc, CS8406-DZZ Datasheet - Page 39

• Manufacturer Part Number: CS8406-DZZ
• Description: IC XMITTER DGTL 192KHZ 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Transmitterr

Specifications of CS8406-DZZ

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Audio Control Type: Digital
• Control Interface: 3 Wire, Serial
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 3.14V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1722

DS580F5
16.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which allows the user to
manage the C and U data through the control port.
16.1
16.1.1 Accessing the E buffer
MANAGEMENT
AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the
control port.
The CS8406 manages the flow of channel status data at the block level, meaning that entire blocks of chan-
nel status information are buffered at the input, synchronized to the output timebase, and then transmitted.
The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in
The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0
(which is at control port address 20h) is the consumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used
as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer.
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS8406, through the control port. The user can modify the data to be transmitted by writing
to the E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever “E to F” buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this
bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in
after a E to F transfer, which is based on the output timebase.
If the channel status block to transmit indicates PRO Mode, then the CRCC byte is automatically calcu-
lated by the CS8406, and does not have to be written into the last byte of the block by the host microcon-
Figure 17. Channel Status Data Buffer Structure
8-bits
A
C ontrol Port
w ords
E
8-bits
24
B
Transm it
D ata
Buffer
F
To
AE S3
Transm itter
Figure
18. For writing, the sequence starts
CS8406
Figure
17.
39