ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 278

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
I
I
R245 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bits 7:6,4 = FREQ[2:0] Frequency bits.
IMPORTANT: To guarantee correct operation,
set these bits before enabling the interface
(while I2CCR.PE=0).
These bits can be set only when the interface is
disabled (I2CCR.PE=0). To configure the interface
to I
sponding to the microcontroller internal frequency
INTCLK.
Note: If an incorrect value, with respect to the
MCU internal frequency, is written in these bits,
the timings of the peripheral will not meet the I
bus standard requirements.
Note: The FREQ[2:0] = 100, 101, 110, 111 config-
urations must not be used.
Bit 5 = EN10BIT Enable 10-bit I
When this bit is set, the 10-bit I
abled.
This bit can be written only when the peripheral is
disabled (I2CCR.PE=0).
0: 7-bit mode selected
1: 10-bit mode selected
Bits 4:3 = Reserved.
Bits 2:1 = ADD[9:8] Interface address.
These are the most significant bits of the I
address of the interface (10-bit mode only). They
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FREQ1 FREQ0 EN10BIT FREQ2
9
2
2
C BUS INTERFACE (Cont’d)
C OWN ADDRESS REGISTER 2 (I2COAR2)
7
INTCLK
Range
14 - 24
2
2.5 - 6
10- 14
(MHz)
6- 10
C specified delays, select the value corre-
FREQ2
0
0
0
0
FREQ1
0
0
0
1
1
2
2
Cbus mode is en-
ADD9 ADD8
Cbus mode.
FREQ0
0
1
0
1
2
Cbus
0
0
2
C
are not cleared when the interface is disabled
(I2CCR.PE=0).
Bit 0 = Reserved.
I
R246 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bits 7:0 = DR[7:0] I2C Data.
– In transmitter mode:
– In receiver mode:
GENERAL CALL ADDRESS (I2CADR)
R247 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 1010 0000 (A0h)
Bits 7:0 = ADR[7:0] Interface address.
These bits define the I
of the interface. It must be written with the correct
value depending on the use of the peripheral.If the
peripheral is used in I
must be loaded as General Call address.
The customer could load the register with other
values.
The bits can be written only when the peripheral is
disabled (I2CCR.PE=0)
The ADR0 bit is don’t care; the interface acknowl-
edges either 0 or 1.
Note: Address 01h is always ignored.
2
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
DR7
C DATA REGISTER (I2CDR)
I2CDR contains the next byte of data to be trans-
mitted. The byte transmission begins after the
microcontroller has written in I2CDR or on the
next rising edge of the clock if DMA is complete.
I2CDR contains the last byte of data received.
The next byte receipt begins after the I2CDR
read by the microcontroller or on the next rising
edge of the clock if DMA is complete.
7
7
DR6
DR5
DR4
2
2
C bus mode, the 00h value
Cbus General Call address
DR3
DR2
DR1
DR0
0
0