ST92150JDV1QAuto STMicroelectronics, ST92150JDV1QAuto Datasheet - Page 420

• Manufacturer Part Number: ST92150JDV1QAuto
• Description: 8/16-bit single voltage Flash MCU family with RAM, E3 TM(emulated EEPROM), CAN 2.0B and J1850 BLPD
• Manufacturer: STMicroelectronics

Specifications of ST92150JDV1QAuto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
KNOWN LIMITATIONS (Cont’d)
13.7 MFT DMA MASK BIT RESET WHEN MFT0
DMA PRIORITY LEVEL IS SET TO 0
Introduction
The MultiFunction Timer is a 16-bit timer with Input
Capture and Output Compare modes. In Input
Capture mode, the timer value is saved when an
external event occurs. In Output Compare mode,
the timer changes an I/O pin level when it reaches
the Compare Register value.
In these two modes the event (Input Capture or
Output Compare) may generate an interrupt or re-
quest a Direct Memory Access.
– In interrupt Input Capture mode (or Output Com-
– In DMA mode these transfers are done automat-
The choice between Interrupt or DMA modes is
defined by the CP0D and CM0D bits (bit 6 and bit
3 in the IDMR register, R255 page 10/8).
CP0D : Capture 0 DMA Mask. Capture on REG0R
DMA is enabled when CP0D = 1.
CM0D: Compare 0 DMA Mask. Compare on
CMP0R DMA is enabled when CM0D = 1.
In DMA mode a DMA counter register and a DMA
address register define the location and the size of
420/430
1
pare mode), the interrupt routine saves the coun-
ter in the RAM or the Register File (or updates
the compare register from a location in RAM or
in the Register File).
ically.
the memory block (RAM or Reg. File) involved in
these transfers.
Each DMA transfer decreases the counter value.
When the counter reaches 0, an EndOfBlock
event occurs on the DMA controller. This event is
detected by the MFT which resets the CP0D or the
CM0D bit.
Limitation Description
The MFT1 resets its DMA Mask bit even if the
End-of-Block signal is dedicated to the MFT0.
This limitation occurs if the following conditions are
fulfilled:
– a MFT DMA request (for instance MFT1) occurs
– the MFT0 DMA request corresponds to an End-
– the MFT0 DMA priority level is set to 0.
This limitation is due to wrong End-of-Block event
management by the MFT, it does not impact the
SCI and the I2C but they can be involved in the
limitation if:
– First peripheral requests a DMA transfer with
– Other peripherals request a DMA transfer with a
End-of-Block event,
higher priority level between the same two DMA
arbitrations. As a consequence, the MFT1 DMA
request is not serviced and a DMA transfer is
lost. This is also true for a Top Level Interrupt
(higher priority than DMA).
while another peripheral DMA request is being
serviced (for instance MFT0),
of-Block