TDA9989ET/C1,551 NXP Semiconductors, TDA9989ET/C1,551 Datasheet
TDA9989ET/C1,551
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TDA9989ET/C1,551 Summary of contents
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TDA9989 150 MHz pixel rate HDMI 1.3a transmitter with 3 inputs and CEC support Rev. 02 — 11 June 2009 1. General description The TDA9989 is a very low power and very small size High-Definition Multimedia Interface (HDMI) 1.3a transmitter. ...
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... NXP Semiconductors Fig 1. TDA9989 high-level block diagram 2. Features I Compliance N DVI 1.0 N HDMI 1.3a N EIA/CEA-861B N CEC (HDMI 1.3a) N SimplayHD I Video N xvYCC HDMI 1.3a feature N Video formats with a pixel rate up to 150 MHz: RGB YCbCr YCbCr semi planar YCbCr ITU656 N Maximum resolution: 1080p for TV ...
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... NXP Semiconductors N Master DDC-bus interface for EDID read N Controllable via I N Downstream availability through the use of hot plug (HPD) and receiver detection (RxSense) N Deals with multiple levels of receivers and repeaters I Package N TFBGA64 N Size 4.5 I Power management N External voltage supplies 1.8 V, 1.2 V (to support 1080p video format, the 1.2 V must be raised to 1 ...
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AUDIO PROCESSING ACLK FIFO AUDIO CONTENT AUDIO AP1 CAPTURE PROCESSING WS CTS/N PLL BLOCK CLOCK VCLK MANAGEMENT 3 8-bit RGB or YCbCr 12-bit YCbCr semi-planar VSYNC/VREF HSYNC/VREF VIDEO DE/FREF ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. 6.2 Pin description Table 2. Symbol ACLK AP0 AP1 HPD EXT_SWING DSDA DSCL VCLK HSYNC/HREF VSYNC/VREF DE/FREF CSCL CSDA INT_HDMI TX0 TX0+ TX1 TDA9989_2 Product data sheet ball A1 1 index area Pin configuration (TFBGA64) ...
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... NXP Semiconductors Table 2. Symbol TX1+ TX2 TX2+ TXC TXC+ CEC OSC_IN OSC_OUT VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] V DDA(TMDS)(1V8) V DDD(IO)(1V8) V DDA(PLL)(1V8) ...
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... NXP Semiconductors Table 2. Symbol V DDDC V SSD V SSA [ power supply ground input output. [2] To support 1080p video format, the 1.2 V supply voltage must be raised to 1 Functional description The TDA9989 is designed to convert digital data (video and audio) provided by Set-Top Boxes (STB), Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP) or DVD into an HDMI output, which can be used with either an HDMI or DVI input ...
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... NXP Semiconductors The TDA9989 can accept any of the following video input modes (see • RGB, with 8-bit for each component • YCbCr with 8-bit for each component • YCbCr semi-planar, with up to 12-bit for each component (YCbCr) • YCbCr ITU656, with up to 12-bit data depth The TDA9989 can be set to latch data at either rising or falling edge, or both ...
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... NXP Semiconductors Table 3. Internal assignment Internal port VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0] The device can swap and invert, in the event of a little endian stream, the incoming video data using I 00h) to match the expectation of the video processing block. ...
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... NXP Semiconductors Table 4. Video input swap to VP[23:20] External SWAP_A assignment selector value Pin Pin number name A4 VPA[7] 100b B4 VPA[6] A3 VPA[5] B3 VPA[4] A2 VPA[3] 101b B2 VPA[2] B1 VPA[1] C1 VPA[0] In the same way: • SWAP_B is used to map incoming video port to the internal port VP[19:16]. • ...
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... NXP Semiconductors Table 5. Bit setting MIRR_E = 1 SWAP_E = 5 MIRR_F = 1 SWAP_F = 4 When input ports are not used possible to map them to internal ground via the 2 I C-bus with the appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on page 00h. TDA9989_2 Product data sheet TDA9989 input/output capability ...
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Input format mappings Table 6 gives more information concerning input format supported. Table 6. Inputs of video input formatter Color Format Channels Sync type Rising space edge RGB 8-bit external X embedded X ...
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... NXP Semiconductors 7.2.3.1 RGB external synchronization (rising edge) Table 7. RGB (3 8-bit) external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Video port B Pin RGB Pin VPA[0] B[0] VPB[0] VPA[1] B[1] VPB[1] VPA[2] B[2] VPB[2] VPA[3] ...
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... NXP Semiconductors VCLK HSYNC/HREF CONTROL VSYNC/VREF INPUTS DE/FREF VPA[7:0] Cb [7:0] 0 VPB[7:0] Y [7:0] 0 VPC[7:0] Cr [7: could also be generated from HSYNC/HREF and VSYNC/VREF. Fig 6. Pixel encoding YCbCr external synchronization input (rising edge) 7.2.3.3 YCbCr ITU656-like external synchronization (rising edge) Table 9. YCbCr ITU656-like external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h ...
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... NXP Semiconductors 7.2.3.4 YCbCr ITU656-like external synchronization (rising and falling edge) Table 10. YCbCr ITU656-like external synchronization input (rising and falling edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] Cb[0] Y [0] Cr[0] 0 VPA[1] Cb[1] Y [1] ...
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... NXP Semiconductors 7.2.3.5 YCbCr ITU656-like embedded synchronization (rising edge) Table 11. YCbCr ITU656-like embedded synchronization input (rising edge) mappings Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] Cb[0] Y [0] Cr[0] 0 VPA[1] Cb[1] Y [1] Cr[1] 0 VPA[2] Cb[2] Y [2] ...
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... NXP Semiconductors 7.2.3.6 YCbCr ITU656-like embedded synchronization (rising and falling edge) Table 12. YCbCr ITU656-like embedded synchronization input (rising and falling edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr (ITU656-like) VPA[0] Cb[0] Y [0] Cr[0] 0 VPA[1] Cb[1] Y [1] ...
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... NXP Semiconductors 7.2.3.7 YCbCr semi-planar external synchronization (rising edge) Table 13. YCbCr semi-planar external synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin YCbCr Pin semi-planar VPA[0] Y [0] Y [0] VPB[ VPA[1] Y [1] Y [1] VPB[1] ...
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... NXP Semiconductors 7.2.3.8 YCbCr semi-planar embedded synchronization (rising edge) Table 14. YCbCr semi-planar embedded synchronization input (rising edge) mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Video port B Pin YCbCr Pin semi-planar VPA[0] Y [0] Y [0] VPB[ VPA[1] Y [1] Y [1] VPB[1] ...
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... NXP Semiconductors 7.3 Input and output video format Due to the flexible video input formatter, the TDA9989 can accept a large range of input formats. This flexibility allows the TDA9989 to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler, downsampler) before it is transmitted across the HDMI link ...
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... NXP Semiconductors Remark: Gamut-related metadata is an HDMI 1.3a feature. 7.7 Downsampler This block works only with YCbCr input format; the filters downsample the Cb and Cr signals by a factor delay is added on the Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel. ...
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... NXP Semiconductors word select a. Philips format. word select b. Left justified format. word select c. Right justified format. Fig 13 The I S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency f Audio samples with a precision better than 24-bit are truncated to 24-bit ...
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... NXP Semiconductors 7.8.3 Audio port internal assignment The aim of the internal audio input assignment is to internally map any of the incoming data from the audio port AP1 to I appropriate I Fig 14. Audio input swap to I 7.9 Power management The TDA9989 HDMI and CEC cores can be independently powered down by the I register ...
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... NXP Semiconductors 7.10 Interrupt controller Pin INT_HDMI is used to alert the micro controller that a critical event concerning the HDMI or CEC has occurred. The software provided with the device read a status register 2 (I C-bus) to determine which block between HDMI and CEC has caused the interruption before processing it ...
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... NXP Semiconductors As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set to logic 1. As soon as the cable is unplugged or receiver side powered off (assuming in this case that V is switched off), the RxSense generates an interrupt inside the TDA9989, changing CC the value of bit RXS_FIL to logic 0 (See sending unnecessary video content ...
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... NXP Semiconductors 7.11.2 Clock CEC clock must be running in Sleep mode (with CEC) to wake up the TDA9989 using CEC specific message as described in “HDMI 1.3a specification” . CEC module can be clocked using: • External clocks: – 12 MHz crystal. – 12 MHz to 50 MHz clock available on PCB • ...
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... NXP Semiconductors Non successful calibration will lead to CEC signal no matching timings specification as consequence CEC not functional. 7.11.3 CEC interrupt Pin INT_HDMI is used by the TDA9989 to warm the host processor HDMI or CEC events (CEC message is available to read) have occurred. Software reads interrupt status register determine which block between HDMI or CEC has raised the interruption before processing it ...
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... NXP Semiconductors Table 20. PR[ others 7.12.3 DDC-bus channel The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode (100 kHz). The DDC-bus is used as a master interface when reading the EDID. When the device is power-off DSDA and DSCL ports: • ...
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... NXP Semiconductors C-bus interface and register definitions 2 8.1 I C-bus protocol 2 The I C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The registers of the TDA9989 can be accessed via the I except for those which are confidential. ...
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... NXP Semiconductors The CEC core does not need memory page mechanism due to its reduced number of registers. 8.3 ID version The ID version readable via I and VERSION registers.The ID version value is 131h. 8.4 Clock stretching Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction cannot continue until the line is released HIGH again ...
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... NXP Semiconductors Table 23. Input format …continued L: recommend tied to LOW voltage Input pins Signal RGB VPB[6] Y[6]/G[6] G[6] VPB[7] Y[7]/G[7] G[7] Video port C VPC[0] Cr[0]/R[0] R[0] VPC[1] Cr[1]/R[1] R[1] VPC[2] Cr[2]/R[2] R[2] VPC[3] Cr[3]/R[3] R[3] VPC[4] ...
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... NXP Semiconductors Table 24. Timing parameters for EIA/CEA-861B EIA/CEA-861B Format Video code 10, 11 2880 480i 12, 13 2880 240p 12, 13 2880 240p 14, 15 1440 480p 16 1920 1080p 50 Hz systems 17, 18 720 576p 19 1280 720p 20 1920 1080i 21, 22 (PAL) 1440 576i 23, 24 1440 288p ...
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... NXP Semiconductors Table 26. Timing parameters for PC standards below 150 MHz Standard Format 640 350p 640 400p 720 400p 0.31M3 640 480p VGA 640 480p 640 480p 640 480p 0.48M3 800 600p SVGA 800 600p 800 600p 800 600p 800 600p 0.48M3-R ...
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... NXP Semiconductors Table 26. Timing parameters for PC standards below 150 MHz Standard Format 1.29MA-R 1440 900p 1.29MA 1440 900p 1440 900p 1.76MA-R 1680 1050p 1.76MA 1680 1050p 10. Limiting values Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol ...
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... NXP Semiconductors Table 29. Supplies …continued +85 C; unless otherwise specified. amb Symbol Parameter V PLL analog supply voltage (1.8 V) DDA(PLL)(1V8) V analog supply voltage (1.8 V) DDA(1V8) V CEC oscillator supply voltage DD(OSC)(CEC) I digital supply current (1.8 V) DDD(1V8) I TMDS analog supply current (1.8V) ...
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... NXP Semiconductors Table 30. Digital inputs and outputs +85 C; unless otherwise specified. amb Symbol Parameter 5 V tolerant input pin HPD V LOW-level input voltage IL V HIGH-level input voltage IH C input capacitance i CMOS 1.8 V and CMOS 3.3 V tolerant digital input/output pin INT_HDMI V LOW-level input voltage ...
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... NXP Semiconductors Table 31. Timing characteristics +85 C; unless otherwise specified. amb Symbol Parameter DDC-bus: pins DSDA, DSCL (5 V tolerant) master bus f SCL frequency SCL C capacitance for each I/O pin C-bus: pins CSCL, CSDA (5 V tolerant) slave bus f SCL frequency SCL t stretch time ...
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... NXP Semiconductors DE, HSYNC, VSYNC Fig 19. Set-up and hold time definition diagram for double-edge clock mode 14. Application information 14.1 Transmitter connection with external world Figure 20, TDA9989 can be part of a repeater application as described in “HDMI 1.3a specification” . Fig 20. Connecting TDA9989 transmitter using external oscillator for CEC ...
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... NXP Semiconductors Fig 21. Connecting TDA9989 transmitter using external clock source Fig 22. Connecting TDA9989 transmitter using internal FRO for CEC TDA9989_2 Product data sheet TRANSMITTER SIDE 2 I C-bus video 24-bit MASTER 2 sync I C-BUS MAIN SLAVE audio PROCESSOR TDA9989 OSC_IN EXTERNAL CLOCK DDC ...
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... NXP Semiconductors 15. Package outline TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.10 0.30 0.80 mm nom 0.95 0.25 0.70 min 0.85 0.20 0.65 OUTLINE VERSION IEC SOT962 Fig 23 ...
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... NXP Semiconductors 16. Abbreviations Table 32. Acronym AC3 ACP ACR ATSC AV BOM CEA CEC CTS/N DDC DDR DE DSC DTS DTV DVC DVD DVI EAV EDID E-EDID EIA FIFO FREF FRO HBM HDCP HDMI HPD HREF HSYNC LSB LV-CMOS MPEG MSB PC PCB PCM PLL ...
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... NXP Semiconductors Table 32. Acronym PMP POR RGB SAV SDR SMPTE S/PDIF STB TMDS UM PC UXGA60 VHREF VREF VSYNC YCbCr WS TDA9989_2 Product data sheet Abbreviations …continued Description Portable Multimedia Player Power-On Reset R = red green blue Start Active Video Single Data Rate Society of Motion Picture and Television Engineers ...
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... NXP Semiconductors 17. Revision history Table 33. Revision history Document ID Release date TDA9989_2 20090611 • Modifications: Table • Table • Table • Clock frequency maximum: changed 165 MHz to 150 MHz TDA9989_1 20090225 TDA9989_2 Product data sheet Data sheet status Product data sheet ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors TDA9989_2 Product data sheet HDMI 1.3a transmitter with CEC support Notes Rev. 02 — 11 June 2009 TDA9989 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 21. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Internal assignment . . . . . . . . . . . . . . . . . . . . . .8 Table 4. Video input swap to VP[23:20 Table 5. TDA9989 input/output capability . . . . . . . . . . .10 Table 6. Inputs of video input formatter . . . . . . . . . . . . .12 Table 7. RGB (3 ¥ 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . .13 Table 8. YCbCr ¥ 8-bit) external synchronization input (rising edge) mapping ...
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... NXP Semiconductors 22. Figures Fig 1. TDA9989 high-level block diagram Fig 2. TDA9989 Block diagram . . . . . . . . . . . . . . . . . . . .4 Fig 3. Pin configuration (TFBGA64 Fig 4. Internal assignment of VP[23:0 Fig 5. Pixel encoding RGB external synchronization input (rising edge .13 Fig 6. Pixel encoding YCbCr external synchronization input (rising edge .14 Fig 7. Pixel encoding YCbCr ITU656-like external synchronization input (rising edge) ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 System clock 7.2 Video input formatter . . . . . . . . . . . . . . . . . . . . 7 7.2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.2 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8 7.2.3 Input format mappings . . . . . . . . . . . . . . . . . . 12 7 ...